Patents by Inventor Chih-Wei Hsiao
Chih-Wei Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961791Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.Type: GrantFiled: May 18, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Wen Hsiao, Ming-Da Cheng, Chih-Wei Lin, Chen-Shien Chen, Chih-Hua Chen, Chen-Cheng Kuo
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Publication number: 20240113113Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
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Publication number: 20240080984Abstract: A package structure, including a circuit board, multiple circuit structure layers, at least one bridge structure, and at least one supporting structure, is provided. The circuit structure layer is disposed on the circuit board. The bridge structure is connected between the two adjacent circuit structure layers. The supporting structure is located between the two adjacent circuit structure layers, and the supporting structure has a first end and a second end opposite to each other and respectively connecting the bridge structure and the circuit board.Type: ApplicationFiled: January 3, 2023Publication date: March 7, 2024Applicant: Industrial Technology Research InstituteInventors: Yu-Wei Huang, Ching-Feng Yu, Chih-Cheng Hsiao
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Publication number: 20240079981Abstract: A motor drive system includes an electric motor, a drive circuit and a control unit. The drive circuit provides a driving current to the electric motor. A current command generator of the control unit generates a current command according to a torque command and a motor operating information. The driving current is converted into a d-axis current and/or a q-axis current by the control unit. Consequently, the driving current is close to the d-axis current command and/or the q-axis current command corresponding to the current command. If a value of the torque command is positive, the current command generator generates the corresponding current command according to a MTPA lookup table. If the value of the torque command is negative, the current command generator generates the corresponding current command according to a zero recycle lookup table.Type: ApplicationFiled: December 2, 2022Publication date: March 7, 2024Inventors: Chih-Hung Hsiao, Chung-Hsing Ku, Shang-Wei Chiu, Zhi-Sheng Yang
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Publication number: 20230185628Abstract: One or more computer processors determine a runtime feature set for a first container, wherein the runtime feature set includes aggregated temporally collocated container behavior. The one or more computer processors cluster the first container with one or more peer containers or peer pods based on a shared container purpose, similar container behaviors, and similar container file structure. The one or more computer processors determine an additional runtime feature set for each peer container. The one or more computer processors calculate a variance between the first container and each peer container. The one or more computer processors, responsive to the calculated variance exceeding a variance threshold, identify the first container as anomalous.Type: ApplicationFiled: December 13, 2021Publication date: June 15, 2023Inventors: Yun-Chang Lo, Chun-Shuo Lin, Chih-Wei Hsiao, Wei-Hsiang Hsiung, WEI-JIE LIAU
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Patent number: 11121871Abstract: A technique to secure a wireless communication link that is being shared among a wireless access point (AP), and each of a set of wireless clients (each a mobile station (STA)) that are coupled to the AP over the communication link. A typical implementation is a WPA2-PSK communication link. In this approach, and in lieu of a single secret key being shared by all AP-STA pairs, each AP-STA pair derives its own unique WLAN shared secret, preferably via a Diffie-Hellman (DH) key exchange. The WLAN shared secret is then used to generate WPA2-PSK keys, namely, pairwise master key (PMK) and pairwise transient key (PTK), that establish an 802.11 standards-compliant secure link.Type: GrantFiled: October 22, 2018Date of Patent: September 14, 2021Assignee: International Business Machines CorporationInventors: Chih-Wei Hsiao, Chih-Wen Chao, Wei-Hsiang Hsiung, Ya-Hsuan Tsai
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Patent number: 11032708Abstract: Securing public hotspot communications by: generating a public-private key pair, deriving an SSID using the generated public key, creating a network using the SSID, specifying a network security setting, and providing a Client the SSID and network security settings. Further, by: receiving a network connection request from the Client, establishing a connection with the Client, receiving a probe request from a network access point, sending an authentication message, receiving SSID configuration information from the network access point, associating the SSID network and the network access point, and receiving Client data.Type: GrantFiled: September 26, 2018Date of Patent: June 8, 2021Assignee: International Business Machines CorporationInventors: Chih-Wei Hsiao, Wei-Hsiang Hsiung, Chih-Wen Chao, Sheng Hao Wang
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Publication number: 20200127829Abstract: A technique to secure a wireless communication link that is being shared among a wireless access point (AP), and each of a set of wireless clients (each a mobile station (STA)) that are coupled to the AP over the communication link. A typical implementation is a WPA2-PSK communication link. In this approach, and in lieu of a single secret key being shared by all AP-STA pairs, each AP-STA pair derives its own unique WLAN shared secret, preferably via a Diffie-Hellman (DH) key exchange. The WLAN shared secret is then used to generate WPA2-PSK keys, namely, pairwise master key (PMK) and pairwise transient key (PTK), that establish an 802.11 standards-compliant secure link.Type: ApplicationFiled: October 22, 2018Publication date: April 23, 2020Applicant: International Business Machines CorporationInventors: Chih-Wei Hsiao, Chih-Wen Chao, Wei-Hsiang Hsiung, Ya-Hsuan Tsai
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Publication number: 20200100107Abstract: Securing public hotspot communications by: generating a public-private key pair, deriving an SSID using the generated public key, creating a network using the SSID, specifying a network security setting, and providing a Client the SSID and network security settings. Further, by: receiving a network connection request from the Client, establishing a connection with the Client, receiving a probe request from a network access point, sending an authentication message, receiving SSID configuration information from the network access point, associating the SSID network and the network access point, and receiving Client data.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Inventors: Chih-Wei Hsiao, Wei-Hsiang Hsiung, Chih-Wen Chao, Sheng Hao Wang
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Patent number: 8976550Abstract: A power supply having a power protection circuit has a rectification circuit and a converter. An input terminal of the rectification circuit is connected with the AC mains. A first voltage dependent resistor is connected with the AC mains. The converter has a transformer. A primary side of the transformer is connected with an output terminal of the rectification circuit, and the secondary side is connected to a power output terminal and a ground terminal. A Y capacitor is connected between the primary side of the transformer and the ground terminal. A surge protection module is connected between the first voltage dependent resistor and the Y capacitor. When a surge occurs between the primary and secondary sides of the transformer, a surge current is shunted by the surge protection module to the ground terminal through the Y capacitor without damaging internal components or circuits inside the power supply.Type: GrantFiled: August 18, 2011Date of Patent: March 10, 2015Assignee: Cyber Power Systems Inc.Inventors: Chih-Wei Hsiao, Yuan-Liang Hsu
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Publication number: 20130044523Abstract: A power supply having a power protection circuit has a rectification circuit and a converter. An input terminal of the rectification circuit is connected with the AC mains. A first voltage dependent resistor is connected with the AC mains. The converter has a transformer. A primary side of the transformer is connected with an output terminal of the rectification circuit, and the secondary side is connected to a power output terminal and a ground terminal. A Y capacitor is connected between the primary side of the transformer and the ground terminal. A surge protection module is connected between the first voltage dependent resistor and the Y capacitor. When a surge occurs between the primary and secondary sides of the transformer, a surge current is shunted by the surge protection module to the ground terminal through the Y capacitor without damaging internal components or circuits inside the power supply.Type: ApplicationFiled: August 18, 2011Publication date: February 21, 2013Inventors: Chih-Wei Hsiao, Yuan-Liang Hsu
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Patent number: 8233296Abstract: A front-end circuit of a power converter has a power connection wiring detecting circuit, a power switch and a control unit. The power connection wiring detecting circuit is connected to an AC power. The control unit is connected to the power connection wiring detecting circuit. The power switch is connected to the power loop. The control unit turns on or off the AC power loop through the power switch. When the power connection wiring is correctly connected with the AC power, the control unit turns on the power switch and the front-end circuit outputs the AC power to the back-end circuit. When the power connection wiring is incorrectly connected with the AC power, the control unit turns off the power switch and the AC power is not outputted to the back-end circuit.Type: GrantFiled: August 26, 2009Date of Patent: July 31, 2012Assignee: Cyber Power System Inc.Inventors: Yuan-Liang Hsu, Han-Yang Huang, Chih-Wei Hsiao
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Publication number: 20110051477Abstract: A front-end circuit of a power converter has a power connection wiring detecting circuit, a power switch and a control unit. The power connection wiring detecting circuit is connected to an AC power. The control unit is connected to the power connection wiring detecting circuit. The power switch is connected to the power loop. The control unit turns on or off the AC power loop through the power switch. When the power connection wiring is correctly connected with the AC power, the control unit turns on the power switch and the front-end circuit outputs the AC power to the back-end circuit. When the power connection wiring is incorrectly connected with the AC power, the control unit turns off the power switch and the AC power is not outputted to the back-end circuit.Type: ApplicationFiled: August 26, 2009Publication date: March 3, 2011Inventors: Yuan-Liang Hsu, Han-Yang Huang, Chih-Wei Hsiao
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Patent number: 7353077Abstract: A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted between at least one arranged field and the alignment mark and inserted adjacent to the wafer edge. The total number of dies manufacturable on the wafer at the first position is determined. The wafer position is shifted to a second position relative to the position of the plurality of fields, and the total number of dies manufacturable on the wafer at the second position is determined. The total number of manufacturable dies from each of the first and the second positions is compared, and the positions having the higher number of manufacturable die are candidates of optimal die placement position. Then the total number of fields, the total number of dummies, and the total number of shared dummies are evaluated to decide the optimal die placement position.Type: GrantFiled: September 8, 2005Date of Patent: April 1, 2008Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chih-Wei Lin, Hong-Hsing Chou, Yeh-Jye Wang, Chen-Fu Chien, Jen-Hsin Wang, Chih-Wei Hsiao
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Publication number: 20070027567Abstract: A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted between at least one arranged field and the alignment mark and inserted adjacent to the wafer edge. The total number of dies manufacturable on the wafer at the first position is determined. The wafer position is shifted to a second position relative to the position of the plurality of fields, and the total number of dies manufacturable on the wafer at the second position is determined. The total number of manufacturable dies from each of the first and the second positions is compared, and the positions having the higher number of manufacturable die are candidates of optimal die placement position. Then the total number of fields, the total number of dummies, and the total number of shared dummies are evaluated to decide the optimal die placement position.Type: ApplicationFiled: September 8, 2005Publication date: February 1, 2007Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Lin, Hong-Hsing Chou, Yeh-Jye Wang, Chen-Fu Chien, Jen-Hsin Wang, Chih-Wei Hsiao