Abstract: A photovoltaic electrochromic device and a method of manufacturing the same are provided. According to the method, at least one thin-film solar cell is formed on a transparent substrate, wherein the thin-film solar cell at least includes an anode, a photoelectric conversion layer, and a cathode, and a portion of a surface of the anode is exposed from the thin film solar cell. An electrochromic thin film is then deposited on at least one surface of the cathode and the exposed surface of the anode. Thereafter, an electrolyte layer is formed on a surface of the thin-film solar cell to cover the electrochromic thin film. The anode and the cathode of the thin-film solar cell also serve as the anode and the cathode of the photovoltaic electrochromic device.

Abstract: A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. Semiconductor units are arranged on a substrate. A material layer is formed on the semiconductor units. A first patterned mask layer is formed on the semiconductor units. The first patterned mask layer has a mask opening corresponding to a portion of the semiconductor units and exposing the material layer. A portion of the material layer exposed by the mask opening is removed to remain a portion of the material layer on a sidewall of each of the semiconductor units exposed by the mask opening to form spacer structures.

Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.

Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate includes a cubic silicon carbon nitride (SiCN) layer. The buffer layer is disposed on the nucleation layer. The nitride semiconductor layer is disposed on the buffer layer.

Abstract: The present invention provides a laminator with a corner cutter including a main body, a laminating device and a cutting device. The main body includes a receiving space. The main body is horizontally formed with an entering slot, an exiting slot, a penetrating groove and a corner-cutting recess. The main body having two lateral sides formed between the entering slot and the exiting slot, the corner-cutting recess being disposed at one of the lateral sides. The laminating device disposed in the receiving space includes two rolling rods, a driving portion and two heaters. The two rolling rods are heated by the two heating members. The driving portion drives the two rolling rods to rotate. The cutting device includes a pushing portion and a cutting portion. The cutting device is disposed at one side of the receiving space where corresponding to the corner-cutting recess.

Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a first buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The first buffer layer is disposed on the nucleation layer. The first buffer layer includes a dopant and Gallium, and an atomic radius of the dopant is larger than an atomic radius of Gallium. The first type nitride semiconductor layer is disposed over the first buffer layer. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer.

Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor stacked layer, a light-emitting layer and a second type nitride semiconductor layer. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor stacked layer is disposed on the buffer layer. The first type nitride semiconductor stacked layer being a plurality of lattice mismatch stacked layers includes a plurality of first nitride semiconductor layers and a plurality of second nitride semiconductor layers. The first nitride semiconductor layers and the second nitride semiconductor layers are stacked alternately, and the first nitride semiconductor layers and the second nitride semiconductor layers are different material. The light-emitting layer is disposed on the first type nitride semiconductor stacked layer.

Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor layer is disposed on the buffer layer. The first type nitride semiconductor layer is doped with a first type dopant, at least one of the buffer layer and the first type nitride semiconductor layer comprises a codopant distributed therein, and an atomic radius of the codopant is larger than an atomic radius of the first type dopant. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer, the second type nitride semiconductor layer comprising a second type dopant.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a plurality of stacked structures and a plurality of contact structures. Each of the stacked structures includes a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. Each of the contact structures is electrically connected to each of the stacked structures. The contact structure includes a first conductive pillar, a dielectric material layer, a metal silicide layer, and a second conductive pillar. The dielectric material layer surrounds the lateral surface of the first conductive pillar. The metal silicide layer is formed on an upper surface of the first conductive pillar. The second conductive pillar is formed on the metal silicide layer. The upper surfaces of the first conductive pillars are coplanar.

Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.

Abstract: A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N?1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W?1 contact openings to create extended contact openings extending to W?1 conductive layers; 2n?1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

Abstract: A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N?1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W?1 contact openings to create extended contact openings extending to W?1 conductive layers; 2n?1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes a base material, a patterned nitride semiconductor, a protection layer, and a nitride semiconductor layer. The patterned nitride semiconductor layer is located on the base material and includes a plurality of nanorod structures and a plurality of block patterns, and an upper surface of the nanorod structures is substantially coplanar with an upper surface of the block patterns. The protection layer covers a side wall of the nanorod structure sand a side wall of the block patterns. The nitride semiconductor layer is located on the patterned nitride semiconductor layer, and a plurality of nanopores are located between the nitride semiconductor layer and the patterned nitride semiconductor layer.

Abstract: An electronic device and a basic input/output system (BIOS) updating device thereof are provided. The electronic device includes a central processing unit (CPU), a chipset, a first interface circuit and a second interface circuit. The chipset is coupled to the CPU. The first interface circuit is coupled to a first memory and a second memory. The first memory includes a first BIOS file and the second memory includes a second BIOS file. The second interface circuit is coupled to the first interface circuit and an external storage device. When the external storage device includes a third BIOS file, a target memory is selected from the first memory and second memory according to a first rule and the target memory is updated using the third BIOS file. Thus, BIOS firmware of the electronic device can be safely updated.

Abstract: An electronic apparatus including a central processing unit (CPU), a chipset, a first interface circuit, a temporary memory, a BIOS (basic input/output system) memory, a second interface circuit and a first switcher is provided. The chipset is coupled to the CPU and the first switcher. The temporary memory is coupled to the first switcher and the first interface circuit. The first interface circuit is coupled to the electronic apparatus and an extended storage including a first BIOS. The second interface circuit is coupled to the first switcher and the BIOS memory. If the first BIOS is stored in the temporary memory, the temporary memory is coupled to the chipset by the first switcher; if the first BIOS is not stored in the temporary memory, the second interface circuit is coupled to the chipset by the first switcher. The electronic device can safely updates the BIOS.

Abstract: The present invention provides a laminator with a corner cutter including a main body, a laminating device and a cutting device. The main body includes a receiving space. The main body is horizontally formed with an entering slot, an exiting slot, a penetrating groove and a corner-cutting recess. The main body having two lateral sides formed between the entering slot and the exiting slot, the corner-cutting recess being disposed at one of the lateral sides. The laminating device disposed in the receiving space includes two rolling rods, a driving portion and two heaters. The two rolling rods are heated by the two heating members. The driving portion drives the two rolling rods to rotate. The cutting device includes a pushing portion and a cutting portion. The cutting device is disposed at one side of the receiving space where corresponding to the corner-cutting recess.

Abstract: A nitride semiconductor LED device including an N-type doped layer, an active layer and a P-type doped layer is provided. The active layer is disposed on the N-type doped layer and includes at least one quantum well structure. The quantum well structure includes two quantum barrier layers and a quantum well sandwiched between the quantum barrier layers. The quantum barrier layer is a super-lattice structure including a quaternary nitride semiconductor. The P-type doped layer is disposed on the active layer.

Abstract: A nitride semiconductor LED device including an N-type doped layer, an active layer and a P-type doped layer is provided. The active layer is disposed on the N-type doped layer and includes at least one quantum well structure. The quantum well structure includes two quantum barrier layers and a quantum well sandwiched between the quantum barrier layers. The quantum barrier layer is a super-lattice structure including a quaternary nitride semiconductor. The P-type doped layer is disposed on the active layer.