Abstract: A rectilinear-block placement method includes disposing a first sub-block of each flexible block on a layout area of a chip canvas according to a reference position, generating an edge-depth map relative to first sub-blocks of flexible blocks on the layout area, predicting positions of second sub-blocks of the flexible blocks with depth values on the edge-depth map by a machine learning model, and positioning the second sub-blocks on the layout area according to the predicted positions of the second sub-blocks of the flexible blocks.

Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.

Abstract: A diagnosis circuit comprises: a logic circuit, wherein the logic circuit comprises a set having a gate voltage terminal of an arm of a phase logical OR a dead time voltage terminal, and the set logical XOR a drain-source voltage terminal of another arm of the phase; a filter circuit coupled to the logic circuit, wherein the filter circuit is configured to filter transient noises; a comparison circuit coupled to the filter circuit, wherein the comparison circuit is configured to determine whether a phase current of a phase current terminal of the phase is greater than zero; and a latch coupled to the comparison circuit, wherein the latch is configured to store diagnosis signals temporarily.

Abstract: A soft-switching auxiliary circuit is provided, which may be applicable to a converter including a first main switch and a second main switch. The soft-switching auxiliary circuit may include a first auxiliary switch, a second auxiliary switch, a first energy adjustment module and a second energy adjustment module. By means of the first auxiliary switch and a second auxiliary switch, the first energy adjustment module and the second energy adjustment may properly store and adjust the energy of the converter; therefore, both the first main switch and the second main switch of the converter can achieve soft-switching.

Abstract: A diagnosis circuit comprises: a logic circuit, wherein the logic circuit comprises a set having a gate voltage terminal of an arm of a phase logical OR a dead time voltage terminal, and the set logical XOR a drain-source voltage terminal of another arm of the phase; a filter circuit coupled to the logic circuit, wherein the filter circuit is configured to filter transient noises; a comparison circuit coupled to the filter circuit, wherein the comparison circuit is configured to determine whether a phase current of a phase current terminal of the phase is greater than zero; and a latch coupled to the comparison circuit, wherein the latch is configured to store diagnosis signals temporarily.

Abstract: A soft-switching auxiliary circuit is provided, which may be applicable to a converter including a first main switch and a second main switch. The soft-switching auxiliary circuit may include a first auxiliary switch, a second auxiliary switch, a first energy adjustment module and a second energy adjustment module. By means of the first auxiliary switch and a second auxiliary switch, the first energy adjustment module and the second energy adjustment may properly store and adjust the energy of the converter; therefore, both the first main switch and the second main switch of the converter can achieve soft-switching.

Abstract: A wireless system includes: a paging chip arranged to selectively generate a notification signal according to a paging signal; and a processing chip arranged to switch from a first mode to a second mode upon receiving the notification signal, wherein power consumption of the processing chip in the first mode is lower than power consumption of the processing chip in the second mode, and the paging chip and the processing chip are externally coupled with each other.

Abstract: Methods for generating an embedded target image to be stored in a non-volatile memory device of an embedded system as firmware thereof are disclosed. A graphical user interface (GUI) editor is generated to facilitate a user in providing settings information for multiple pins of a chip installed in the embedded system. Source code is generated in response to operating results of the user of the GUI editor. Linking an object file compiled from the generated source code generates the embedded target image.

Abstract: A system for real time clock (RTC) calibration includes: a timer counter; a clock generator; and a clock calibration unit coupled between the clock generator and the timer counter. The clock calibration unit receives calibration parameters comprising an average calibration value, a remainder calibration value and a calibration period, counts a plurality of clock cycles generated by the clock generator, calibrates a number of the counted clock cycles according to the average calibration value and remainder calibration value in the calibration period, and increments the timer counter by one second when a predetermined number of clock cycles have been reached.

Abstract: A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.

Abstract: A system for real time clock (RTC) calibration includes: a timer counter; a clock generator; and a clock calibration unit coupled between the clock generator and the timer counter. The clock calibration unit receives calibration parameters comprising an average calibration value, a remainder calibration value and a calibration period, counts a plurality of clock cycles generated by the clock generator, calibrates a number of the counted clock cycles according to the average calibration value and remainder calibration value in the calibration period, and increments the timer counter by one second when a predetermined number of clock cycles have been reached.

Abstract: Methods for generating an embedded target image to be stored in a non-volatile memory device of an embedded system as firmware thereof are disclosed. A graphical user interface (GUI) editor is generated to facilitate a user in providing settings information for multiple pins of a chip installed in the embedded system. Source code is generated in response to operating results of the user of the GUI editor. Linking an object file compiled from the generated source code generates the embedded target image.

Abstract: A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.