Patents by Inventor Chih-Wei Kuo

Chih-Wei Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210343538
    Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
  • Patent number: 11130152
    Abstract: A method for the formation of tantalum carbides on a graphite substrate includes the steps of: (a) adding an organic tantalum compound, a chelating agent, a pre-polymer to an organic solvent to form a tantalum polymeric solution; (b) subjecting a graphite substrate with the tantalum polymeric solution to a curing process to form a polymeric tantalum film on the graphite substrate; and (c) subjecting the polymeric tantalum film on the graphite substrate in an oven to a pyrolytic reaction in the presence of a protective gas to obtain a protective tantalum carbide on the graphite substrate.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: September 28, 2021
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Cheng-Jung Ko, Jun-Bin Huang, Chih-Wei Kuo, Dai-Liang Ma, Bang-Ying Yu
  • Publication number: 20210296576
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 23, 2021
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20210288107
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a passivation layer between the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on and directly contacting the passivation layer and around the first MTJ and the second MTJ. Preferably, a top surface of the passivation layer includes a V-shape and a valley point of the V-shape is higher than a bottom surface of the first top electrode.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 11121050
    Abstract: In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Chih-Wei Wu, Li-Chung Kuo, Long Hua Lee, Sung-Hui Huang, Ying-Ching Shih, Pai Yuan Li
  • Patent number: 11119001
    Abstract: A machine tool health monitoring method which is to use a predetermined plurality of vibration sensors on a plurality of components of a machine tool and to drive motors of the machine tool to excite the machine tool using an electronic device while the health status of the machine tool is good, and then to perform a diagnostic process to obtain a characteristic cluster consisting of a plurality of modals, and then to define the characteristic cluster as a sample health characteristic cluster. The diagnostic process includes the procedures of vibration transmissibility obtaining, singular value decomposition, curve fitting and modal establishing. In addition, excite the machine tool and proceed the diagnosis process to obtain a current health characteristic cluster. Finally, the current health characteristic cluster is compared with the sample health characteristic cluster to judge whether the machine tool is healthy or not.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 14, 2021
    Assignees: NATIONAL CHUNG CHENG UNIVERSITY, TONGTAI MACHINE & TOOL CO., LTD.
    Inventors: Chih-Chun Cheng, Yu-Sheng Chiu, Wen-Nan Cheng, Ping-Chun Tsai, Yu-Hsin Kuo, Wei-Jen Chen, De-Shin Liu, Chen-Wei Chuang, Chih-Ta Wu, Wen-Peng Tseng, Wen-Chieh Kuo
  • Patent number: 11121307
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 14, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chia-Chang Hsu, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 11101344
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Lin, Chih-Lin Wang, Kang-Min Kuo
  • Patent number: 11101143
    Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer, a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction, and a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer. The source/drain structure includes a SiP layer, and an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yuan-Shun Chao, Chih-Wei Kuo
  • Patent number: 11072871
    Abstract: A preparation apparatus for uniform silicon carbide crystals comprises a circular cylinder, a doping tablet, and a plate to stabilize and control the supply of dopants. The accessory does not participate in the reaction in the growth chamber but maintains its efficacy during growth. Finally, a single semi-insulating silicon carbide crystal with uniform electrical characteristics can be obtained.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 27, 2021
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Chih-Wei Kuo, Dai-Liang Ma, Chia-Hung Tai, Bang-Ying Yu, Cheng-Jung Ko, Bo-Cheng Lin, Hsueh-I Chen
  • Publication number: 20210216429
    Abstract: A diagnostic system applied to an electronic equipment with a plurality of hardware devices is provided. The hardware devices include a display and a processor, the diagnostic system is executed by the processor to diagnose the hardware devices. The diagnostic system includes a diagnostic test interface, which is displayed on the display and includes a plurality of hardware items corresponding to the hardware devices. Each of the hardware items links to the hardware devices. When at least one of the hardware items is triggered, the processor executes the diagnostic item of the hardware device corresponding to the triggered hardware item.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 15, 2021
    Inventors: Kun-Hsin Chiang, Hsin-Hui Huang, Wei-Hsian Chang, Wen-Yen Hsieh, Ming-Yi Huang, Yu-Chieh Chang, Tang-Hui Liao, Chih-Wei Kuo
  • Patent number: 11056536
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20210189590
    Abstract: A preparation apparatus for uniform silicon carbide crystals comprises a circular cylinder, a doping tablet, and a plate to stabilize and control the supply of dopants. The accessory does not participate in the reaction in the growth chamber but maintains its efficacy during growth. Finally, a single semi-insulating silicon carbide crystal with uniform electrical characteristics can be obtained.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: Chih-Wei Kuo, Dai-Liang Ma, Chia-Hung Tai, Bang-Ying Yu, Cheng-Jung Ko, Bo-Cheng Lin, Hsueh-I Chen
  • Publication number: 20210162453
    Abstract: A method for the formation of tantalum carbides on a graphite substrate includes the steps of: (a) adding an organic tantalum compound, a chelating agent, a pre-polymer to an organic solvent to form a tantalum polymeric solution; (b) subjecting a graphite substrate with the tantalum polymeric solution to a curing process to form a polymeric tantalum film on the graphite substrate; and (c) subjecting the polymeric tantalum film on the graphite substrate in an oven to a pyrolytic reaction in the presence of a protective gas to obtain a protective tantalum carbide on the graphite substrate.
    Type: Application
    Filed: November 28, 2019
    Publication date: June 3, 2021
    Inventors: Cheng-Jung Ko, Jun-Bin Huang, Chih-Wei Kuo, Dai-Liang Ma, Bang-Ying Yu
  • Patent number: 10978355
    Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Publication number: 20210057637
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.
    Type: Application
    Filed: September 19, 2019
    Publication date: February 25, 2021
    Inventors: Chih-Wei Kuo, Chia-Chang Hsu, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20210028352
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming an etch stop layer on the first IMD layer; forming a second IMD layer on the etch stop layer; forming a patterned hard mask on the second IMD layer; performing a first etching process to form a contact hole in the second IMD layer for exposing the etch stop layer; performing a second etching process to remove the patterned hard mask; performing a third etching process to remove the etch stop layer and the first IMD layer for exposing the MTJ; and forming a metal interconnection in the contact hole.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 28, 2021
    Inventors: Chih-Wei Kuo, Meng-Jun Wang, Yi-Wei Tseng, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 10903269
    Abstract: A magnetic memory device includes a first dielectric layer on a substrate, first and second via plugs in the first dielectric layer, first and second cylindrical memory stacks on the first and second via plugs, respectively, and an insulating cap layer conformally disposed on the first dielectric layer and on sidewalls of the first and second cylindrical memory stacks. The insulating cap layer is not disposed in a logic area and a via forming region between the first and second cylindrical memory stacks.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: January 26, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20210020693
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.
    Type: Application
    Filed: August 20, 2019
    Publication date: January 21, 2021
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20210013395
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a metal interconnection. The two magnetic tunnel junction elements are arranged side by side at a first direction. The metal interconnection is disposed between the magnetic tunnel junction elements, wherein the metal interconnection includes a contact plug part having a long shape at a top view, and the long shape has a length at a second direction larger than a width at the first direction, wherein the second direction is orthogonal to the first direction.
    Type: Application
    Filed: August 1, 2019
    Publication date: January 14, 2021
    Inventors: Chih-Wei Kuo, Ting-Hsiang Huang, Yu-Tsung Lai, Jiunn-Hsiung Liao