Abstract: A manufacturing method of a memory device includes following steps. A memory unit including a first electrode, a second electrode, and a memory material layer is formed on a substrate. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A first spacer layer including a first portion, a second portion, and a third portion is formed on a sidewall of the memory unit. The first portion is disposed on a sidewall of the first electrode. The second portion is disposed on a sidewall of the second electrode. The third portion is disposed above the memory unit in the vertical direction and connected with the second portion. A thickness of the second portion in a horizontal direction is greater than that of the first portion in the horizontal direction.

Abstract: A bathtub overflow pipe structure includes an overflow pipe which includes an outlet end formed to an L-shaped end of the overflow pipe. An adaptor includes a passage defined axially therethrough which communicates with the first outlet of the overflow pipe. A first flange extends radially outward from one end of the adaptor to contact the outside wall of the bathtub. The outer periphery of the adaptor is detachably connected to the passage by threading engagement. A cover includes a cap and a column extends axially from the cap. A second outlet is defined axially in the column and communicates with the passage. The column includes two overflow holes. A ring is mounted to the outer periphery of the column which is inserted into the passage. The ring contacts against the inner periphery of the passage to combine the cover to the overflow pipe via the adaptor without any screw.

Abstract: A resistive memory device includes a dielectric layer, a trench, a first resistive switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer. The first resistive switching element is disposed in the trench. The first resistive switching element includes a first bottom electrode, a first top electrode disposed above the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode. The diode via structure is disposed in the dielectric layer and located under the trench, and the diode via structure is connected with the first bottom electrode. The signal line structure is disposed in the trench, a part of the signal line structure is disposed on the first resistive switching element, and the signal line structure is electrically connected with the first top electrode.

Abstract: Some implementations described herein include operating components in a lithography system at variable speeds to reduce, minimize, and/or prevent particle generation due to rubbing of or collision between contact parts of the components. In some implementations, a component in a path of transfer of a semiconductor substrate in the lithography system is operated at a relatively high movement speed through a first portion of an actuation operation, and is operated at a reduced movement speed (e.g., a movement speed that is less than the high movement speed) through a second portion of the actuation operation in which contact parts of the component are to interact. The reduced movement speed reduces the likelihood of particle generation and/or release from the contact parts when the contact parts interact, while the high movement speed provides a high semiconductor substrate throughput in the lithography system.

Abstract: A heat dissipation device is provided and includes: a first vapor chamber filled with a first working fluid therein and used for contacting at least one heat source; at least one heat transfer structure disposed on a side of the first vapor chamber; and a second vapor chamber filled with a second working fluid therein and connected to the first vapor chamber via the heat transfer structure, where the first working fluid absorbs heat of the heat source and then vaporizes, and the vaporized first working fluid transfers the heat to the second working fluid via the heat transfer structure.

Abstract: Pellicles are inspected by projecting a light pattern thereon and monitoring the reflected light by CCD module or the like. Software-based inspection of the reflected pattern recognizes any distortions in the pattern or contamination, and thus identifies wrinkles or other defects in the pellicle prior to use in the manufacturing process. Recognition of defects and replacement will avoid instances of pellicle rupture thereby avoiding damage to wafers being patterned.

Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.

Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

Abstract: In certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.

Abstract: A method includes forming a first fin structure and a second fin structure protruding from a substrate, forming a dielectric fin between the first fin structure and the second fin structure, recessing the dielectric fin to form a trench between the first fin structure and the second fin structure, and depositing a first dielectric layer on sidewall surfaces of the trench and on a top surface of the recessed dielectric fin. After the depositing the first dielectric layer, a second dielectric layer is deposited in the trench. The method further includes depositing a third dielectric layer to cap the second dielectric layer in the trench, and forming a gate structure on the first fin structure, the second fin structure, and the third dielectric layer.

Abstract: A lifting module for a chassis and an electronic device including the lifting module are provided. The lifting module includes a sidewall bracket, a lifting bracket, a sliding button assembly, and a driven assembly. The sidewall bracket is disposed on a side frame of the chassis. The lifting bracket is movably connected to the sidewall bracket. The sliding button assembly is slidably disposed on the side frame of the chassis. Part of the sliding button assembly is exposed from the chassis. The driven assembly is movably disposed on the sidewall bracket. The driven assembly is connected to interact the sliding button assembly and the lifting bracket. The lifting bracket is driven to move relative to the sidewall bracket selectively by the sliding button assembly through the driven assembly.

Abstract: In certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.

Abstract: Embodiments of the disclosure provide a method for resetting a processor and a computer device. The method includes: obtaining an image file corresponding to a coprocessor by a first component of the computer device, and loading the image file into a reference space in a RAM by the first component; loading the image file stored in the reference space into a specific space corresponding to the coprocessor by a second component of the computer device and validating the image file stored in the specific space by the second component in response to determining that the coprocessor needs to be reset; and resetting the coprocessor by the second component based on the image file stored in the specific space in response to the second component determining that the image file stored in the specific space is valid.

Abstract: A semiconductor device includes a pair of fin structures on a semiconductor substrate, each including a vertically stacked plurality of channel layers, a dielectric fin extending in parallel to and between the fin structures, and a gate structure on and extending perpendicularly to the fin structures, the gate structure engaging with the plurality of channel layers. The dielectric fin includes a fin bottom and a fin top over the fin bottom. The fin bottom has a top surface extending above a bottom surface of a topmost channel layer. The fin top includes a core and a shell, the core having a first dielectric material, the shell surrounding the core and having a second dielectric material different from the first dielectric material.

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

Abstract: A semiconductor device includes a substrate, a first MTJ structure, a second MTJ structure, an interconnection structure including a first metal interconnection and a second metal interconnection disposed on and contacting the first metal interconnection, a fifth metal interconnection, and a sixth metal interconnection. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction. The fifth metal interconnection and the sixth metal interconnection are disposed under and contact the first MTJ structure and the second MTJ structure, respectively. The fifth metal interconnection includes a barrier layer and a metal layer disposed on the barrier layer. A length of the first MTJ structure in the first horizontal direction is greater than a length of the metal layer in the first horizontal direction.

Abstract: A power supply circuit and a power distribution method thereof are provided. The power supply circuit includes a power input switch block, a power supply measurement block, a power supply conversion block and a power supply control block. The power input switch block provides a first power supply voltage to a load circuit based on an external power supply voltage from an adapter. The power supply measurement block measures a current of the first power supply voltage. The power supply conversion block is coupled to the battery module to provide a second power supply voltage to the load circuit. When a battery temperature of the battery module is higher than a critical temperature and a battery power of the battery module is higher than or equal to a critical power, the power supply control block limits the second power supply voltage provided to the load circuit.

Abstract: A method for preparing a carbide protective layer comprises: (A) mixing a carbide powder, an organic binder, an organic solvent and a sintering aid to form a slurry; (B) spraying the slurry on a surface of a graphite component to form a composite component; (C) subjecting the composite component to a cold isostatic pressing densification process; (D) subjecting the composite component to a constant temperature heat treatment; (E) repeating steps (B)-(D) until a coating is formed on a surface of the composite component; (F) subjecting the coating to a segmented sintering process; (G) obtaining a carbide protective layer used for the surface of the composite component. Accordingly, while the carbide protective layer can be completed by using the wet cold isostatic pressing densification process and the cyclic multiple superimposition method, so that it can improve the corrosion resistance in the silicon carbide crystal growth process environment.