Patents by Inventor Chih-Wei Kuo

Chih-Wei Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12255196
    Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Patent number: 12245521
    Abstract: A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: March 4, 2025
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Wei Kuo, Chung Yi Chiu, Yi-Wei Tseng, Hsuan-Hsu Chen, Chun-Lung Chen
  • Publication number: 20250053103
    Abstract: Some implementations described herein include operating components in a lithography system at variable speeds to reduce, minimize, and/or prevent particle generation due to rubbing of or collision between contact parts of the components. In some implementations, a component in a path of transfer of a semiconductor substrate in the lithography system is operated at a relatively high movement speed through a first portion of an actuation operation, and is operated at a reduced movement speed (e.g., a movement speed that is less than the high movement speed) through a second portion of the actuation operation in which contact parts of the component are to interact. The reduced movement speed reduces the likelihood of particle generation and/or release from the contact parts when the contact parts interact, while the high movement speed provides a high semiconductor substrate throughput in the lithography system.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Shao-Hua WANG, Kueilin HO, Cheng Wei SUN, Zong-You YANG, Chih-Chun CHIANG, Yi-Fam SHIU, Chueh-Chi KUO, Heng-Hsin LIU, Li-Jui CHEN
  • Publication number: 20250052044
    Abstract: A bathtub overflow pipe includes an overflow pipe, an adapter and a over. The overflow pipe includes an extending section with an outlet. The adapter is connected to the end face of the extending section of the overflow pipe by bolts. The adapter includes a sleeve and a tab extending radially from one end of the sleeve. The sleeve includes a passage and is inserted into the outlet of the overflow pipe. The tab has a recess formed to its lower edge and communicating with the outlet for drainage. The cover includes a pillar and a rim which has a recessed area. The pillar extends axially from one of two sides of the cover and has a rib. The pillar extends through the passage of the adapter, the rib is slidably engaged with the recessed rail. The cover, the adapter and the overflow pipe can be precisely and easily assembled.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Inventors: KUANG-MING KUO, CHIH-WEI CHEN
  • Patent number: 12213389
    Abstract: A memory device includes a substrate, a memory unit disposed on the substrate, a first spacer layer, and a second spacer layer. The memory unit includes a first electrode, a second electrode disposed above the first electrode, and a memory material layer disposed between the first electrode and the second electrode. The first spacer layer is disposed on a sidewall of the memory unit and includes a first portion disposed on a sidewall of the first electrode, a second portion disposed on a sidewall of the second electrode, and a bottom portion. A thickness of the second portion is greater than that of the first portion. The second spacer layer is disposed on the first spacer layer. A material composition of the second spacer layer is different from that of the first spacer layer. The bottom portion is disposed between the substrate and the second spacer layer.
    Type: Grant
    Filed: August 28, 2023
    Date of Patent: January 28, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chung-Yi Chiu
  • Patent number: 12189442
    Abstract: A method for detecting heat dissipation is provided, including the following steps: sensing a core temperature of a heat emitting component of an electronic device; sensing current power of the heat emitting component when the core temperature is greater than or equal to a warning temperature; and transmitting an assembling check prompt and activating a thermal control circuit (TCC) when the current power is less than thermal design power (TDP) of the heat emitting component. An electronic device is further provided, to execute the method for detecting heat dissipation.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: January 7, 2025
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Kun-Hsin Chiang, Yu-Chieh Chang, Tang-Hui Liao, Wei-Hsian Chang, Wen-Yen Hsieh, Chih-Wei Kuo, Ming-Yi Huang, Ching-Chan Chu, Shun-Po Chang
  • Patent number: 12193342
    Abstract: A manufacturing method of a memory device includes following steps. A memory unit including a first electrode, a second electrode, and a memory material layer is formed on a substrate. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A first spacer layer including a first portion, a second portion, and a third portion is formed on a sidewall of the memory unit. The first portion is disposed on a sidewall of the first electrode. The second portion is disposed on a sidewall of the second electrode. The third portion is disposed above the memory unit in the vertical direction and connected with the second portion. A thickness of the second portion in a horizontal direction is greater than that of the first portion in the horizontal direction.
    Type: Grant
    Filed: August 28, 2023
    Date of Patent: January 7, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chung-Yi Chiu
  • Publication number: 20240422989
    Abstract: A resistive memory device includes a dielectric layer, a trench, a first resistive switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer. The first resistive switching element is disposed in the trench. The first resistive switching element includes a first bottom electrode, a first top electrode disposed above the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode. The diode via structure is disposed in the dielectric layer and located under the trench, and the diode via structure is connected with the first bottom electrode. The signal line structure is disposed in the trench, a part of the signal line structure is disposed on the first resistive switching element, and the signal line structure is electrically connected with the first top electrode.
    Type: Application
    Filed: July 18, 2023
    Publication date: December 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chung-Yi Chiu
  • Publication number: 20240365493
    Abstract: A lifting module for a chassis and an electronic device including the lifting module are provided. The lifting module includes a sidewall bracket, a lifting bracket, a sliding button assembly, and a driven assembly. The sidewall bracket is disposed on a side frame of the chassis. The lifting bracket is movably connected to the sidewall bracket. The sliding button assembly is slidably disposed on the side frame of the chassis. Part of the sliding button assembly is exposed from the chassis. The driven assembly is movably disposed on the sidewall bracket. The driven assembly is connected to interact the sliding button assembly and the lifting bracket. The lifting bracket is driven to move relative to the sidewall bracket selectively by the sliding button assembly through the driven assembly.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 31, 2024
    Applicant: Wistron Corporation
    Inventors: Yin Tseng Lu, Chih Wei Kuo, YUCHUN HUNG, Tsung Han Yu, Hsiang Wen Huang, Chen Wei Tsai
  • Publication number: 20240315146
    Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.
    Type: Application
    Filed: May 26, 2024
    Publication date: September 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chia-Chang Hsu
  • Patent number: 12096697
    Abstract: A semiconductor device includes a substrate, a first MTJ structure, a second MTJ structure, an interconnection structure including a first metal interconnection and a second metal interconnection disposed on and contacting the first metal interconnection, a fifth metal interconnection, and a sixth metal interconnection. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction. The fifth metal interconnection and the sixth metal interconnection are disposed under and contact the first MTJ structure and the second MTJ structure, respectively. The fifth metal interconnection includes a barrier layer and a metal layer disposed on the barrier layer. A length of the first MTJ structure in the first horizontal direction is greater than a length of the metal layer in the first horizontal direction.
    Type: Grant
    Filed: October 18, 2023
    Date of Patent: September 17, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chia-Chang Hsu
  • Patent number: 12084388
    Abstract: A method for preparing a carbide protective layer comprises: (A) mixing a carbide powder, an organic binder, an organic solvent and a sintering aid to form a slurry; (B) spraying the slurry on a surface of a graphite component to form a composite component; (C) subjecting the composite component to a cold isostatic pressing densification process; (D) subjecting the composite component to a constant temperature heat treatment; (E) repeating steps (B)-(D) until a coating is formed on a surface of the composite component; (F) subjecting the coating to a segmented sintering process; (G) obtaining a carbide protective layer used for the surface of the composite component. Accordingly, while the carbide protective layer can be completed by using the wet cold isostatic pressing densification process and the cyclic multiple superimposition method, so that it can improve the corrosion resistance in the silicon carbide crystal growth process environment.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: September 10, 2024
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Chih-Hsing Wang, Cheng-Jung Ko, Chuen-Ming Gee, Chih-Wei Kuo, Hsueh-I Chen, Jun-Bin Huang, Ying-Tsung Chao
  • Publication number: 20240239712
    Abstract: A method for preparing a carbide protective layer comprises: (A) mixing a carbide powder, an organic binder, an organic solvent and a sintering aid to form a slurry; (B) spraying the slurry on a surface of a graphite component to form a composite component; (C) subjecting the composite component to a cold isostatic pressing densification process; (D) subjecting the composite component to a constant temperature heat treatment; (E) repeating steps (B)-(D) until a coating is formed on a surface of the composite component; (F) subjecting the coating to a segmented sintering process; (G) obtaining a carbide protective layer used for the surface of the composite component. Accordingly, while the carbide protective layer can be completed by using the wet cold isostatic pressing densification process and the cyclic multiple superimposition method, so that it can improve the corrosion resistance in the silicon carbide crystal growth process environment.
    Type: Application
    Filed: January 13, 2023
    Publication date: July 18, 2024
    Inventors: CHIH-HSING WANG, CHENG-JUNG KO, CHUEN-MING GEE, CHIH-WEI KUO, HSUEH-I CHEN, JUN-BIN HUANG, YING-TSUNG CHAO
  • Publication number: 20240229858
    Abstract: An electronic device includes a monitor stand, a hinge mechanism, and an operation element. The hinge mechanism includes a back plate, a speed reduction assembly, and a friction assembly. The back plate is fixed to the monitor stand. The speed reduction assembly includes an input plate and a speed reduction member. The speed reduction member is arranged on the input plate. The friction assembly is arranged between the back plate and the input plate. The operation element is connected to the speed reduction member. A rotation center of the operation element coincides with an axis of the back plate and the speed reduction member are coaxially arranged.
    Type: Application
    Filed: January 17, 2023
    Publication date: July 11, 2024
    Inventors: Chih-Wei KUO, Yu-Chun HUNG, Che-Yen CHOU, Chen-Wei TSAI, Hsiang-Wen HUANG
  • Patent number: 12029138
    Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: July 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chia-Chang Hsu
  • Patent number: 12022739
    Abstract: A method for forming a semiconductor device includes the steps of providing a substrate having a memory region and a logic region, forming a memory stack structure on the memory region, forming a passivation layer covering a top surface and sidewalls of the memory stack structure, forming a first interlayer dielectric layer on the passivation layer, performing a post-polishing etching back process to remove a portion of the first interlayer dielectric layer and a portion of the passivation layer on the top surface of the memory stack structure, forming a second interlayer dielectric layer on the first interlayer dielectric layer and directly contacting the passivation layer, and forming an upper contact structure through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure to contact the memory stack structure.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: June 25, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chih-Wei Kuo
  • Patent number: 12010923
    Abstract: A semiconductor device includes a substrate having a logic region and a memory region, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer disposed on and directly contacting a top surface of the first interlayer dielectric layer. A portion of the top surface of the first interlayer dielectric layer on the memory region is lower than another portion of the top surface of the first interlayer dielectric layer on the logic region. A memory stack structure is disposed in the first interlayer dielectric layer on the memory region. A passivation layer covers a top surface and sidewalls of the memory stack structure and is in direct contact with the second interlayer dielectric layer. An upper contact structure penetrates through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure and directly contacts the memory stack structure.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: June 11, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chih-Wei Kuo
  • Patent number: 12010926
    Abstract: A method of manufacturing a magnetic tunnel junction (MTJ) device, including steps of forming a dielectric layer comprising a metal line therein on a substrate, forming a magnetic tunneling junction element over the metal line, depositing a silicon nitride cap layer conformally covering the magnetic tunneling junction element and the dielectric layer, depositing a tantalum containing cap layer conformally covering the silicon nitride cap layer, removing parts of the tantalum containing cap layer and the silicon nitride cap layer, and disposing a metal plug directly on the magnetic tunneling junction element.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: June 11, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chih-Wei Kuo
  • Patent number: 11994970
    Abstract: A diagnostic system applied to an electronic equipment with a plurality of hardware devices is provided. The hardware devices include a display and a processor, the diagnostic system is executed by the processor to diagnose the hardware devices. The diagnostic system includes a diagnostic test interface, which is displayed on the display and includes a plurality of hardware items corresponding to the hardware devices. Each of the hardware items links to the hardware devices. When at least one of the hardware items is triggered, the processor executes the diagnostic item of the hardware device corresponding to the triggered hardware item.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 28, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Kun-Hsin Chiang, Hsin-Hui Huang, Wei-Hsian Chang, Wen-Yen Hsieh, Ming-Yi Huang, Yu-Chieh Chang, Tang-Hui Liao, Chih-Wei Kuo
  • Publication number: 20240133421
    Abstract: An electronic device includes a monitor stand, a hinge mechanism, and an operation element. The hinge mechanism includes a back plate, a speed reduction assembly, and a friction assembly. The back plate is fixed to the monitor stand. The speed reduction assembly includes an input plate and a speed reduction member. The speed reduction member is arranged on the input plate. The friction assembly is arranged between the back plate and the input plate. The operation element is connected to the speed reduction member. A rotation center of the operation element coincides with an axis of the back plate and the speed reduction member are coaxially arranged.
    Type: Application
    Filed: January 17, 2023
    Publication date: April 25, 2024
    Inventors: Chih-Wei KUO, Yu-Chun HUNG, Che-Yen CHOU, Chen-Wei TSAI, Hsiang-Wen HUANG