Patents by Inventor Chih-Wei Lai
Chih-Wei Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250128263Abstract: A moving device, applied in a nucleic acid extraction system and cooperated with a plurality of microtube components, the moving device includes: a workbench; a moving component, disposed on the workbench; a control element, disposed on the moving component and electrically connected to the moving component; a first motor, disposed on the moving component and electrically connected to the control element; a first rotating rod, connected to the first motor; a second motor, disposed on the moving component and electrically connected to the control element; a second rotating rod, connected to the second motor; and a telescopic component, disposed on the moving component corresponding to the first rotating rod and the second rotating rod, electrically connected to the control element, and movable between a first position and a second position.Type: ApplicationFiled: March 15, 2024Publication date: April 24, 2025Inventors: Chung-Che LO, Shan-Yi YEN, Yi-Chi WANG, Nien-Ting CHEN, Chih-Wei LAI
-
Publication number: 20250086937Abstract: An image recognition system for a neural network and an image preprocessing method are provided. The image recognition system includes a memory, an image sensor, a preprocessing circuit, and a neural network processing member. The image sensor is configured to obtain an image that includes a plurality of pixels. The preprocessing is configured to classify each pixel based on the division criterion and the rotation angle as belonging to at least one of the target sub-images, and calculate a memory address corresponding to the pixel in the target sub-image to which the pixel belongs, so as to sequentially store the plurality of target sub-images in the memory. The neural network processing member is configured to retrieve one of the stored target sub-images from the memory for recognition.Type: ApplicationFiled: July 16, 2024Publication date: March 13, 2025Inventor: Chih-Wei LAI
-
Patent number: 12199073Abstract: The present disclosure provides a micro light emitting diode display including a metal substrate, a plurality of micro light emitting diode chips on the metal substrate, a plurality of light absorbing layers on the metal substrate between the micro light emitting diode chips, a light conversion layer above the micro light emitting diode chips, and a cover plate above the light conversion layer, where sidewalls of the micro light emitting diode chips are separated by a gap, and where a contact angle of the light absorbing layers is between 0 degree and 30 degrees.Type: GrantFiled: January 20, 2022Date of Patent: January 14, 2025Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (ShenZhen) Co., Ltd., General Interface Solution LimitedInventors: Chih-Wei Lai, Hui-Ping Shen
-
Patent number: 12139292Abstract: A clamping device is applied to a cover of a container and comprises a first gear plate having a first rail hole, a second gear plate having a second rail hole, a guiding plate configured between the first gear plate and the second gear plate and having a guiding slot, a first motor, a second motor and a clamp assembly. The first motor is configured to drive the first gear plate to rotate. The second motor is configured to drive the second gear plate to rotate. The clamp component of the clamp assembly is disposed in the first rail hole, the second rail hole and the guiding slot and configured to contact the cover. The first motor and the second motor drive the first gear plate and the second gear plate to rotate in opposite directions and drive the clamp component to move inwardly for clamping the cover.Type: GrantFiled: September 7, 2023Date of Patent: November 12, 2024Assignee: ARISE BIOTECH CORPORATIONInventors: Te-Hua Lee, Chung-Che Lo, Chih-Wei Lai
-
Publication number: 20240372515Abstract: The present disclosure discloses a differential inductor circuit is provided that includes a first coil inductor and a second coil inductor. The first coil inductor is coupled to a first terminal and starts to extend for a first half circle and further extend to surround an central area for N first full circles to be coupled to a second terminal, wherein N is an integer larger than or equal to 0. The second coil inductor is coupled to a third terminal to and starts to extend for a second half circle and further extend to surround the central area for N second full circles to be coupled to a fourth terminal, in which the second half circle and the first half circuit together enclose the central area.Type: ApplicationFiled: April 29, 2024Publication date: November 7, 2024Inventor: Chih-Wei Lai
-
Publication number: 20240278947Abstract: A clamping device is applied to a cover of a container and comprises a first gear plate having a first rail hole, a second gear plate having a second rail hole, a guiding plate configured between the first gear plate and the second gear plate and having a guiding slot, a first motor, a second motor and a clamp assembly. The first motor is configured to drive the first gear plate to rotate. The second motor is configured to drive the second gear plate to rotate. The clamp component of the clamp assembly is disposed in the first rail hole, the second rail hole and the guiding slot and configured to contact the cover. The first motor and the second motor drive the first gear plate and the second gear plate to rotate in opposite directions and drive the clamp component to move inwardly for clamping the cover.Type: ApplicationFiled: September 7, 2023Publication date: August 22, 2024Inventors: TE-HUA LEE, CHUNG-CHE LO, CHIH-WEI LAI
-
Publication number: 20240159878Abstract: A range detection device and a method for range detection thereof are disclosed. An optical sensing element receives a reflected signal of external light signal for triggering a transformation element to generate an electrical signal of receiving detection. Range detection data are generated to an operation processing unit according to the electrical signal of receiving detection and an electrical signal of reference. A plurality of first item data of the range detection data are compressed and operated to generate a plurality of first operation data to be stored as stored data. Further, the first item data correspond to a plurality of first storage addresses. The first operation data correspond to a plurality of second storage addresses. A first address amount of the first storage addresses is greater than a second address amount of the second storage addresses. Thereby, more storage addresses will be spared and hence extending the detection range.Type: ApplicationFiled: November 14, 2023Publication date: May 16, 2024Inventor: Chih-Wei Lai
-
Publication number: 20240039065Abstract: A battery module including a battery frame, a plurality of locking structures, a plurality of battery units, and a plurality of lug structures is provided. The battery frame is provided with an accommodating space. The battery frame includes a first portion extending along a first direction and a second portion extending along a second direction. The first direction is different from the second direction. The locking structures are disposed on the battery frame. At least one of the plurality of locking structures is disposed on an outer side of each of the first portion and the second portion. The battery units are disposed in the accommodating space. Each of the lug structures includes a lock portion configured to detachably engage with one of the locking structures.Type: ApplicationFiled: February 21, 2023Publication date: February 1, 2024Inventors: Po-Ching HUANG, Hui Wen CHIU, Chun-Wen WANG, Pao-Long FAN, Cheng-Ping TSAI, Ting-Jui HU, Chao Chan TAN, Ming-Hung YAO, Chien-Chih SHIH, Jui-Liang HO, Ching-Kai YU, Chih-Wei LAI
-
Publication number: 20240022068Abstract: An ESD circuit includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a first ESD current path, a second ESD current path, a biasing circuit and a control circuit. The control circuit is connected between the pad and a first node. The first P-type transistor is connected with the pad, the control circuit and a second node. The first ESD current path is connected between the second node and the first node. The second ESD current path is connected between the second node and the first node. The second P-type transistor is connected with the pad, the control circuit and a third node. The biasing circuit is connected between the third node and the first node. The third P-type transistor is connected with the pad, the third node, and a fourth node. The internal circuit is connected between the fourth node and the first node.Type: ApplicationFiled: May 9, 2023Publication date: January 18, 2024Inventors: Yun-Jen Ting, Chih-Wei LAI, Yi-Han WU, Kun-Hsin LIN, Hsin-Kun HSU
-
Publication number: 20230178521Abstract: The present disclosure provides a micro light emitting diode display including a metal substrate, a plurality of micro light emitting diode chips on the metal substrate, a plurality of light absorbing layers on the metal substrate between the micro light emitting diode chips, a light conversion layer above the micro light emitting diode chips, and a cover plate above the light conversion layer, where sidewalls of the micro light emitting diode chips are separated by a gap, and where a contact angle of the light absorbing layers is between 0 degree and 30 degrees.Type: ApplicationFiled: January 20, 2022Publication date: June 8, 2023Inventors: Chih-Wei LAI, Hui-Ping SHEN
-
Patent number: 11616360Abstract: An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.Type: GrantFiled: September 22, 2021Date of Patent: March 28, 2023Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chih-Wei Lai, Yun-Jen Ting, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
-
Patent number: 11508719Abstract: An ESD circuit is connected between an I/O pad and a first node. The ESD circuit includes a bi-directional buck circuit, a triggering circuit and a discharging circuit. The bi-directional buck circuit includes a forward path and a reverse path. The forward path and the reverse path are connected between the I/O pad and a second node. The triggering circuit is connected between the second node and the first node. The discharging circuit is connected between the second node and the first node, and connected with the triggering circuit. When the I/O pad receives negative ESD zap, the ESD current flows from the first node to the I/O pad through the discharging circuit and the reverse path. When the I/O pad receives positive ESD zap, the ESD current flows from the I/O pad to the first node through the forward path and the discharging circuit.Type: GrantFiled: March 4, 2020Date of Patent: November 22, 2022Assignee: EMEMORY TECHNOLOGY INC.Inventors: Yun-Jen Ting, Chih-Wei Lai, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
-
Patent number: 11462903Abstract: An ESD circuit includes a voltage division circuit, a RC control circuit and a voltage selection circuit. The voltage division circuit is connected between a first power pad and a first node, and generates a first voltage. The RC control circuit is connected between the first power pad and a second power pad, and generates a second voltage and a third voltage. The voltage selection circuit receives the first voltage and the second voltage, and outputs a fourth voltage. The first transistor and the second transistor are serially connected between the first power pad and the second power pad. A gate terminal of the first transistor receives the first voltage. A gate terminal of the second transistor receives the third voltage. The third transistor is connected with the first power pad and an internal circuit. A gate terminal of the third transistor receives the fourth voltage.Type: GrantFiled: June 10, 2020Date of Patent: October 4, 2022Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chih-Wei Lai, Yun-Jen Ting, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
-
Publication number: 20220158446Abstract: An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.Type: ApplicationFiled: September 22, 2021Publication date: May 19, 2022Inventors: Chih-Wei LAI, Yun-Jen TING, Yi-Han WU, Kun-Hsin LIN, Hsin-Kun HSU
-
Patent number: 11025054Abstract: An electrostatic discharge protection device is provided. A voltage selection circuit selects a voltage having a higher voltage value among a reference voltage and a voltage on a conductive path and supply the selected voltage to a RC latch self-feedback circuit, so that the RC latch self-feedback circuit ties a voltage of an input end of a RC control circuit when the electrostatic discharge does not occur, and disconnect a switch that conducts an electrostatic current.Type: GrantFiled: March 25, 2019Date of Patent: June 1, 2021Assignee: eMemory Technology Inc.Inventors: Yun-Jen Ting, Chih-Wei Lai, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
-
Patent number: 11018925Abstract: An apparatus for use in a polar transmitter to perform distortion estimation and compensation is provided. The apparatus includes a mixing unit, a signal processing unit, an estimation unit and a compensation unit. The mixing unit is configured to mix a test output signal and a frequency down-converting signal to generate a mixed signal. The processing unit is configured to perform signal processing on the mixed signal to generate a processed signal. The estimation unit is configured to perform distortion estimation on the processed signal to generate a distortion estimation result. The compensation unit is configured to perform pre-distortion compensation on input signals of the polar transmitter according to the distortion estimation result.Type: GrantFiled: July 2, 2020Date of Patent: May 25, 2021Assignee: Realtek Semiconductor Corp.Inventors: Yuan-Shuo Chang, Yi-Chang Shih, Chih-Wei Lai
-
Patent number: 10944258Abstract: An ESD circuit is connected to a power pad and a first node. The ESD circuit includes a RC circuit and a first ESD current path. The RC circuit is connected between the power pad and the first node. The RC circuit is capable of providing a first control voltage and a second control voltage. The first ESD current path is connected between the power pad and the first node. When the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path.Type: GrantFiled: February 21, 2019Date of Patent: March 9, 2021Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chih-Wei Lai, Yun-Jen Ting, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
-
Publication number: 20200395752Abstract: An ESD circuit includes a voltage division circuit, a RC control circuit and a voltage selection circuit. The voltage division circuit is connected between a first power pad and a first node, and generates a first voltage. The RC control circuit is connected between the first power pad and a second power pad, and generates a second voltage and a third voltage. The voltage selection circuit receives the first voltage and the second voltage, and outputs a fourth voltage. The first transistor and the second transistor are serially connected between the first power pad and the second power pad. A gate terminal of the first transistor receives the first voltage. A gate terminal of the second transistor receives the third voltage. The third transistor is connected with the first power pad and an internal circuit. A gate terminal of the third transistor receives the fourth voltage.Type: ApplicationFiled: June 10, 2020Publication date: December 17, 2020Inventors: Chih-Wei LAI, Yun-Jen TING, Yi-Han WU, Kun-Hsin LIN, Hsin-Kun HSU
-
Publication number: 20200365578Abstract: An ESD circuit is connected between an I/O pad and a first node. The ESD circuit includes a bi-directional buck circuit, a triggering circuit and a discharging circuit. The bi-directional buck circuit includes a forward path and a reverse path. The forward path and the reverse path are connected between the I/O pad and a second node. The triggering circuit is connected between the second node and the first node. The discharging circuit is connected between the second node and the first node, and connected with the triggering circuit. When the I/O pad receives negative ESD zap, the ESD current flows from the first node to the I/O pad through the discharging circuit and the reverse path. When the I/O pad receives positive ESD zap, the ESD current flows from the I/O pad to the first node through the forward path and the discharging circuit.Type: ApplicationFiled: March 4, 2020Publication date: November 19, 2020Inventors: Yun-Jen TING, Chih-Wei LAI, Yi-Han WU, Kun-Hsin LIN, Hsin-Kun HSU
-
Patent number: 10546619Abstract: An ESD circuit is connected with a pad. The ESD circuit includes a voltage divider, a RC circuit and a path control circuit. The voltage divider is connected between the pad and a first node and provides plural divided voltages. The RC circuit is connected between the pad and the first node. The RC circuit receives the plural divided voltages and provides a control circuit. The path control circuit is connected with the pad and the first node. The path control circuit receives the plural divided voltages and the control voltage. When the pad receives a first ESD zap, the RC circuit controls the path control circuit to turn on a first ESD current path. Consequently, an ESD current flows from the pad to the first node through the first ESD current path.Type: GrantFiled: July 31, 2017Date of Patent: January 28, 2020Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chih-Wei Lai, Yun-Jen Ting, Hsin-Kun Hsu