Abstract: A semiconductor device includes a semiconductor substrate having a first source/drain region, a semiconductor layer, a first floating gate electrode, a first control gate electrode, a second floating gate electrode, a second control gate electrode, and an erase gate electrode. The semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode laterally surrounds the first semiconductor layer. The first control gate electrode laterally surrounds the first floating gate electrode and the first semiconductor layer. The second floating gate electrode laterally surrounds the first semiconductor layer. The second control gate electrode laterally surrounds the second floating gate electrode and the semiconductor layer.

Abstract: Pellicles are inspected by projecting a light pattern thereon and monitoring the reflected light by CCD module or the like. Software-based inspection of the reflected pattern recognizes any distortions in the pattern or contamination, and thus identifies wrinkles or other defects in the pellicle prior to use in the manufacturing process. Recognition of defects and replacement will avoid instances of pellicle rupture thereby avoiding damage to wafers being patterned.

Abstract: A clamp ring including an inner periphery of increased diameter at locations where inwardly extending tabs are not located reduces the risk a workpiece that is placed in close proximity to the clamp ring or which contacts the clamp ring during processing will stick to the clamp ring.

Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.

Abstract: A chamber of a semiconductor fabrication facility may include a vent port diffuser. The vent port diffuser may include a first tube member configured to couple the vent port diffuser to a vent port of the chamber. The vent port diffuser may include a second tube member coupled to the first tube member. The second tube member may comprise a plurality of openings spaced along a length of the second tube member, with the plurality of openings configured to receive a fluid from the chamber. Based on the semiconductor fabrication facility including the vent port diffuser, the chamber may be configured to provide an improved flow field of a fluid within the chamber. In this way, the vent port diffuser may reduce defects of semiconductor devices transported through the chamber that might otherwise be caused by contaminants.

Abstract: Methods and systems for chemical vapor deposition (CVD) are disclosed. The methods and systems use a showerhead including a domed internal baffle plate. The domed internal baffle plate is perforated. The presence of the domed internal baffle plate improves the uniformity of gas distribution through the holes of the showerhead across the surface area of the showerhead. This improves deposition uniformity on the semiconducting wafer substrate upon which CVD is being performed, or improves the cleaning of the reaction chamber when a cleaning gas is pumped in through the showerhead.

Abstract: A semiconductor structure includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a second conductive layer arranged within the dielectric layer and electrically connected to the first conductive layer, the second conductive layer including a sidewall distant from the dielectric layer by a width; and a first blocking layer over a surface of the first conductive layer between the second conducive layer and the dielectric layer. The first blocking layer includes at least one element of a precipitant.

Abstract: In certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.

Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

Abstract: A diaphragm position of a valve may be detected and/or determined such that operation of the diaphragm may be monitored. A sensor included in the valve may generate sensor data that may be used to monitor the position of the diaphragm, which in turn may be used to determine a flow of a fluid through the valve. In this way, the sensor may be used to determine whether the diaphragm is properly functioning, may be used to identify and detect failures of the diaphragm, and/or may be used to quickly terminate operation of an associated deposition tool. This may reduce semiconductor substrate scrap, may reduce device failures on semiconductor substrates that are processed by the deposition tool, may increase semiconductor processing quality of the deposition tool, and/or may increase semiconductor processing yields of the deposition tool.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a first floating gate electrode, a first control gate electrode, an erase gate electrode, and a blocking layer. The semiconductor substrate has a first source/drain region. The first semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode surrounds the first semiconductor layer. The first control gate electrode surrounds the first floating gate electrode and the first semiconductor layer. The erase gate electrode is over the first floating gate electrode and the first control gate electrode. The erase gate electrode surrounds the first semiconductor layer. The blocking layer has a first portion between the first floating gate electrode and the first control gate electrode and a second portion between the erase gate electrode and the first semiconductor layer.

Abstract: A clamp ring including an inner periphery of increased diameter at locations where inwardly extending tabs are not located reduces the risk a workpiece that is placed in close proximity to the clamp ring or which contacts the clamp ring during processing will stick to the clamp ring.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: A process tool including a polishing pad on a top surface of a wafer platen. A wafer carrier is configured to hold a wafer over the polishing pad. A slurry dispenser is configured to dispense an abrasive slurry including a plurality of charged abrasive particles having a first polarity onto the polishing pad. A first conductive rod is within the wafer platen and coupled to a first voltage supply. A wafer roller is configured to support the wafer. A first wafer brush is arranged beside the wafer roller. A second conductive rod is within the first wafer brush and coupled to a second voltage supply. The first voltage supply is configured to apply a first charge having a second polarity, opposite the first polarity, to the first conductive rod. The second voltage supply is configured to apply a second charge having the second polarity to the second conductive rod.

Abstract: A method includes forming a first fin structure and a second fin structure protruding from a substrate, forming a dielectric fin between the first fin structure and the second fin structure, recessing the dielectric fin to form a trench between the first fin structure and the second fin structure, and depositing a first dielectric layer on sidewall surfaces of the trench and on a top surface of the recessed dielectric fin. After the depositing the first dielectric layer, a second dielectric layer is deposited in the trench. The method further includes depositing a third dielectric layer to cap the second dielectric layer in the trench, and forming a gate structure on the first fin structure, the second fin structure, and the third dielectric layer.

Abstract: A method of manufacturing an integrated circuit includes following operations. A stack of a plurality pair of first layers and second layers alternately arranged is formed over a substrate. A plurality of first holes is formed in the stack. An isolation layer is formed to cover sidewalls of the first holes. A plurality of conductive features is formed in the first holes. A plurality of second holes are formed in the stack. Each of the second holes exposes a portion of a sidewall of at least one of the conductive features. A channel layer is formed to cover sidewalls of the second holes and the portions of the sidewalls of the conductive features. The second layers of the stack are replaced with a plurality of gate layers.

Abstract: A heat dissipation device includes an inclined heat pipe and a plurality of inclined heat dissipation fins. The inclined heat pipe includes an inclined heat dissipation area, and each inclined heat dissipation fin includes an inclined heat dissipation portion. In addition, the inclined heat dissipation area of the inclined heat pipe is fixed to the inclined heat dissipation portion so that the inclined heat dissipation area of the inclined heat pipe forms a predetermined angle relative to a horizontal plane.

Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.

Abstract: A diaphragm position of a valve may be detected and/or determined such that operation of the diaphragm may be monitored. A sensor included in the valve may generate sensor data that may be used to monitor the position of the diaphragm, which in turn may be used to determine a flow of a fluid through the valve. In this way, the sensor may be used to determine whether the diaphragm is properly functioning, may be used to identify and detect failures of the diaphragm, and/or may be used to quickly terminate operation of an associated deposition tool. This may reduce semiconductor substrate scrap, may reduce device failures on semiconductor substrates that are processed by the deposition tool, may increase semiconductor processing quality of the deposition tool, and/or may increase semiconductor processing yields of the deposition tool.