Patents by Inventor Chih-Wei Lu

Chih-Wei Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250133800
    Abstract: A semiconductor device includes a MEOL structure and a BEOL structure. The BEOL structure is formed over the MEOL structure and includes a first dielectric layer, a spacer and a conductive portion. The first dielectric layer has a lateral surface and a recess, wherein the recess is recessed with respect to the lateral surface. The spacer is formed the lateral surface and covers an opening of the recess. The conductive portion is formed adjacent to the spacer.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Chih-Wei LU, Cheng-Hao CHEN
  • Publication number: 20250125189
    Abstract: A method for manufacturing an interconnect structure includes: forming a first dielectric layer; forming a mask; patterning the first dielectric layer through the mask to form a trench, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 17, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Chih-Wei LU, Hwei-Jay CHU, Yu-Teng DAI, Hsin-Chieh YAO, Yung-Hsu WU, Li-Ling SU, Chia-Wei SU, Hsin-Ping CHEN
  • Publication number: 20250125251
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, strained layers, source/drain contact patterns, a gate contact via, and source/drain contact vias. The gate structure is disposed over the semiconductor substrate. The strained layers are disposed aside the gate structure. The source/drain contact patterns are disposed on and electrically connected to the strained layers. Top surfaces of the source/drain contact patterns are coplanar with a top surface of the gate structure. The gate contact via is disposed on and electrically connected to the gate structure. The source/drain contact vias are disposed on and electrically connected to the source/drain contact patterns.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ling Su, Chia-Wei Su, Tsu-Chun Kuo, Wei-Hao Liao, Hsin-Ping Chen, Yung-Hsu Wu, Ming-Han Lee, Shin-Yi Yang, Chih Wei LU, Hsi-Wen Tien, Meng-Pei Lu
  • Publication number: 20250118656
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first conductive line, a first conductive via, a second conductive line, and a first barrier layer. The first conductive line is disposed on the substrate. The first conductive via is disposed on the first conductive line. The second conductive line is disposed on the first conductive line. The first barrier layer is disposed between the first conductive via and the second conductive line.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: HWEI-JAY CHU, HSI-WEN TIEN, WEI-HAO LIAO, YU-TENG DAI, HSIN-CHIEH YAO, CHENG-HAO CHEN, CHIH WEI LU
  • Publication number: 20250112087
    Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Tzu-Hui WEI, Chih Wei LU, Chan-Yu LIAO, Li-Ling SU, Chia-Wei SU, Yung-Hsu WU, Hsin-Ping CHEN
  • Patent number: 12266565
    Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue, Yu-Teng Dai, Wei-Hao Liao
  • Patent number: 12261121
    Abstract: A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Patent number: 12243775
    Abstract: In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 12211845
    Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Ku Shen, Chih Wei Lu, Hui-Chi Chen, Jeng-Ya David Yeh
  • Publication number: 20240420994
    Abstract: A semiconductor device includes a substrate, a heat dissipation dielectric layer, a conductive interconnect structure, and a blocking dielectric layer. The heat dissipation dielectric layer is disposed on the substrate and has a thermal conductivity greater than 10 W/mK. The conductive interconnect structure is disposed in the heat dissipation dielectric layer. The blocking dielectric layer is disposed in the heat dissipation dielectric layer to isolate the conductive interconnect structure from the heat dissipation dielectric layer.
    Type: Application
    Filed: June 14, 2023
    Publication date: December 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ling SU, Ming-Hsien LIN, Hsin-Ping CHEN, Shao-Kuan LEE, Cheng-Chin LEE, Yen-Ju WU, Hsin-Yen HUANG, Hsi-Wen TIEN, Chih-Wei LU, Chia-Chen LEE
  • Publication number: 20240412975
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Application
    Filed: June 4, 2024
    Publication date: December 12, 2024
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Publication number: 20240387383
    Abstract: An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and a dielectric foam disposed between the first and second portions of the conductive layer. The dielectric foam includes fluid gaps filled with carbon dioxide gas.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Yu-Teng DAI, Chih-Wei LU, Hsin-Chieh YAO, Chung-Ju LEE
  • Patent number: 12138011
    Abstract: Provided herein are image registration methods comprising providing a wide view image of a target area by a first imager; providing a narrow view image of the target area by a second imager; aligning the narrow view image on the wide view image of the target area; capturing an optical image by an optical imager, wherein the optical imager is configured to locate the optical image in the narrow view image; and displaying the position of the optical image on the narrow view image and the wide view image of the target area; and the systems thereof.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: November 12, 2024
    Assignee: Apollo Medical Optics, Ltd.
    Inventors: Chih Wei Lu, Sung Wei Lu, Jia-Wei Lin, I-Ling Chen, Tuan Shu Ho
  • Publication number: 20240371779
    Abstract: The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Yen Huang, Chia-Tien Wu
  • Publication number: 20240371770
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate, a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect conductive structure arranged within the second interconnect dielectric layer. The interconnect conductive structure includes an outer portion that has a first conductive material. Further, the interconnect conductive structure includes a central portion having outermost sidewalls surrounded by the outer portion of the interconnect conductive structure. The central portion includes a second conductive material different than the first conductive material.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Yu-Teng Dai, Hsi-Wen Tien, Wei-Hao Liao, Hsin-Chieh Yao, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 12125795
    Abstract: The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Yen Huang, Chia-Tien Wu
  • Publication number: 20240339396
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 12094823
    Abstract: An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and a dielectric foam disposed between the first and second portions of the conductive layer. The dielectric foam includes fluid gaps filled with carbon dioxide gas.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao, Chung-Ju Lee
  • Patent number: 12074059
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20240282623
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes includes a first insulating layer formed over a semiconductor substrate and conductive vias formed in the first insulating layer. The conductive structure also includes conductive lines and air gaps alternately formed over the first insulating layer. The conductive lines are correspondingly aligned to the conductive vias. The conductive structure further includes capping layers correspondingly covering the plurality of air gaps.
    Type: Application
    Filed: April 29, 2024
    Publication date: August 22, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Chih-Wei LU, Chung-Ju LEE, Shau-Lin SHUE