Patents by Inventor Chih-Wei Mu

Chih-Wei Mu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11146056
    Abstract: An interface control circuit complying with an interface specification includes: an interface signal transceiver circuit and a protection circuit. The interface signal transceiver circuit is coupled to a first interface connection pin and a second interface connection pin of a first interface connector circuit. The interface signal transceiver circuit is for transmitting and/or receiving an interface signal according to the interface specification. When the interface signal transceiver circuit operates under a first state, the protection circuit determines whether a foreign object exists between the first interface connection pin and the second interface connection pin according to a voltage change or a current change at the second interface connection pin. Under the first state, the interface signal transceiver circuit generates a pull-up signal and a pull-down signal which are toggled with each other at the first interface connection pin.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: October 12, 2021
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Yu-Jen Cheng, Chih-Wei Mu, Sheng-Tsung Chen, Chieh-Min Lo, Wei-Chung Chang
  • Publication number: 20210119438
    Abstract: An interface control circuit complying with an interface specification includes: an interface signal transceiver circuit and a protection circuit. The interface signal transceiver circuit is coupled to a first interface connection pin and a second interface connection pin of a first interface connector circuit. The interface signal transceiver circuit is for transmitting and/or receiving an interface signal according to the interface specification. When the interface signal transceiver circuit operates under a first state, the protection circuit determines whether a foreign object exists between the first interface connection pin and the second interface connection pin according to a voltage change or a current change at the second interface connection pin. Under the first state, the interface signal transceiver circuit generates a pull-up signal and a pull-down signal which are toggled with each other at the first interface connection pin.
    Type: Application
    Filed: May 13, 2020
    Publication date: April 22, 2021
    Inventors: Yu-Jen Cheng, Chih-Wei Mu, Sheng-Tsung Chen, Chieh-Min Lo, Wei-Chung Chang
  • Publication number: 20190312426
    Abstract: An interface control circuit includes an interface signal transceiver circuit and a protection circuit. The interface signal transceiver circuit transmits and/or receives an interface signal through a transmission interface which includes at least a first interface pin. The protection circuit includes a switch and a comparison circuit. The switch controls a conduction between the first interface pin and a signal source. The comparison circuit senses a voltage of the first interface pin, and determines whether the voltage of the first interface pin is within a threshold voltage range which corresponds to a foreign object attachment event, whereby the interface signal transceiver circuit is triggered to execute a protection operation.
    Type: Application
    Filed: January 14, 2019
    Publication date: October 10, 2019
    Inventors: Chih-Wei Mu, Chieh-Min Lo, Wei-Chung Chang
  • Patent number: 8368445
    Abstract: A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: February 5, 2013
    Assignee: Faraday Technology Corp.
    Inventors: Chih-Hsien Lin, Chih-Wei Mu, Ming-Shih Yu
  • Publication number: 20130002320
    Abstract: A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Chih-Hsien Lin, Chih-Wei Mu, Ming-Shih Yu