Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

Abstract: A memory device includes an input pad, a first rank, a second rank, a first voltage detector, and a second voltage detector. The input pad is configured to receive an input voltage. The first voltage detector is coupled to the input pad, the first voltage detector is configured to receive the input voltage, and the first voltage detector is configured to transmit the input voltage to the first rank. The second voltage detector is coupled to the first voltage detector through a first through-silicon via, the second voltage detector is configured to receive the input voltage, and the second voltage detector is configured to transmit the input voltage to the second rank according to a control signal transmitted from the first voltage detector through the first voltage detector, so as to decide a state of the second rank.

Abstract: A memory device includes an input pad, a first rank, a second rank, a first voltage detector, and a second voltage detector. The input pad is configured to receive an input voltage. The first voltage detector is coupled to the input pad, the first voltage detector is configured to receive the input voltage, and the first voltage detector is configured to transmit the input voltage to the first rank. The second voltage detector is coupled to the first voltage detector through a first through-silicon via, the second voltage detector is configured to receive the input voltage, and the second voltage detector is configured to transmit the input voltage to the second rank according to a control signal transmitted from the first voltage detector through the first voltage detector, so as to decide a state of the second rank.

Abstract: The memory apparatus includes a plurality of memory chips and a plurality of temperature sensors. The memory chips are coupled to each other. The temperature sensors are respectively disposed on the memory chips. One of the memory chips is configured to be a master memory chip, and a first temperature sensor of the master memory chip is enabled to sense an ambient temperature. The master memory chip generates a refresh rate control signal according to the ambient temperature and controls refresh rates of all of the memory chips.

Abstract: A post package repair (PPR) method is disclosed. The PPR method includes the following operations: receiving a first PPR signal and a second PPR signal, in which the first PPR signal corresponds to a first PPR mode, and the second PPR signal corresponds to a second PPR mode; generating a first valid signal and a second valid signal according to the first PPR signal and the second PPR signal, in which only one of the first valid signal and the second valid signal comprises a valid information when both of the first PPR signal and the second PPR signal comprise an enabled information; in which when the first valid signal comprises the valid information, the first PPR mode is executed, and when the second valid signal comprises the valid information, the second PPR mode is executed.

Abstract: A voltage switching device, an integrated circuit device, and a voltage switching method are provided. The voltage switching device includes a reference voltage generator generating a first reference voltage and a second reference voltage, a fuse system coupled to a circuit device, and a switch circuit coupled to the reference voltage generator, the fuse system, and the circuit device. The fuse system generates a first enable signal and a second enable signal according to an input signal from a circuit device. The switch circuit transmits the first reference voltage or the second reference voltage to the circuit device according to the first enable signal and the second enable signal from the fuse system.

Abstract: The present disclosure provides a memory device. The memory device includes a memory manager, a high-ranking memory and a low-ranking memory, wherein the high-ranking memory and the low-ranking memory are electrically connected to the memory manager. The memory manager replaces information provided by the high-ranking memory with information provided by the low-ranking memory when a swap request is received.

Abstract: The present disclosure provides a dynamic random access device (DRAM). The DRAM includes a first node, a second node and a pad. The first node is configured to conduct a first internal signal generated by internal devices of the DRAM. The second node is configured to conduct a second internal signal generated by other internal devices of the DRAM. The pad is configured to receive one of the first internal signal and the second internal signal.

Abstract: The present disclosure provides a dynamic random access device (DRAM). The DRAM includes a first node, a second node and a pad. The first node is configured to conduct a first internal signal generated by internal devices of the DRAM. The second node is configured to conduct a second internal signal generated by other internal devices of the DRAM. The pad is configured to receive one of the first internal signal and the second internal signal.

Abstract: The present disclosure provides a fuse-blowing system of a dynamic random access memory (DRAM). The fuse-blowing system includes a fuse device and a mapping device. The mapping device, integrated with the fuse device in the DRAM, enables the fuse device and provides the fuse device with a physical address. The enabled fuse device, in response to only the provided physical address, performs a fuse-blowing operation on a fuse of the DRAM.

Abstract: A fuse blowing method is disclosed. The fuse blowing method comprises the following operations: detecting a plurality of voltages of a plurality of word lines; sending an enabling signal to a fuse circuit when one of the voltages is below a voltage threshold, in which the one of the voltages corresponds to one of the word lines; and blowing a fuse, in which the fuse is connected to the one of the word lines, such that the one of the voltages is higher than the voltage threshold.