Patents by Inventor Chih-Wei Shen

Chih-Wei Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10878881
    Abstract: The memory apparatus includes a plurality of memory chips and a plurality of temperature sensors. The memory chips are coupled to each other. The temperature sensors are respectively disposed on the memory chips. One of the memory chips is configured to be a master memory chip, and a first temperature sensor of the master memory chip is enabled to sense an ambient temperature. The master memory chip generates a refresh rate control signal according to the ambient temperature and controls refresh rates of all of the memory chips.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 29, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Wei Shen
  • Patent number: 10811119
    Abstract: A post package repair (PPR) method is disclosed. The PPR method includes the following operations: receiving a first PPR signal and a second PPR signal, in which the first PPR signal corresponds to a first PPR mode, and the second PPR signal corresponds to a second PPR mode; generating a first valid signal and a second valid signal according to the first PPR signal and the second PPR signal, in which only one of the first valid signal and the second valid signal comprises a valid information when both of the first PPR signal and the second PPR signal comprise an enabled information; in which when the first valid signal comprises the valid information, the first PPR mode is executed, and when the second valid signal comprises the valid information, the second PPR mode is executed.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: October 20, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Wei Shen
  • Patent number: 10797048
    Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Chih Wei Lu, Janet Chen, Jeng-Ya David Yeh
  • Publication number: 20200279743
    Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
  • Publication number: 20200264503
    Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Chia-Hao Yu, Chi-Lun Lu, Chih-Tsung Shih, Ching-Wei Shen, Jeng-Horng Chen
  • Patent number: 10734991
    Abstract: A voltage switching device, an integrated circuit device, and a voltage switching method are provided. The voltage switching device includes a reference voltage generator generating a first reference voltage and a second reference voltage, a fuse system coupled to a circuit device, and a switch circuit coupled to the reference voltage generator, the fuse system, and the circuit device. The fuse system generates a first enable signal and a second enable signal according to an input signal from a circuit device. The switch circuit transmits the first reference voltage or the second reference voltage to the circuit device according to the first enable signal and the second enable signal from the fuse system.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: August 4, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Wei Shen
  • Patent number: 10709255
    Abstract: An inflation identification connector and an air mattress system having the same is provided. The inflation identification connector is insertable into a connection seat of a gas delivery host. The connection seat has a light detection component coupled to a controller disposed in the gas delivery host. The inflation identification connector includes a body and an identification structure. The detection result of the light detection component depends on the identification structure and thus is conducive to identification. Upon its insertion into the connection seat, the inflation identification connector is identified by the gas delivery host, enhancing ease of use and protecting manual operation against mistakes. The gas delivery host is not only applicable to different types of air mattresses but also conducive to streamlined management of the air mattress system and reduction of management costs and risks.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 14, 2020
    Assignee: APEX MEDICAL CORP.
    Inventors: David Huang, Wen-Bin Shen, Ju-Chien Cheng, Ming-Heng Hsieh, Fu-Wei Chen, Chih-Kuang Chang, Yi-Ling Liu, Sheng-Wei Lin, Chung-Yi Lin
  • Publication number: 20200201562
    Abstract: The present disclosure provides a memory device. The memory device includes a memory manager, a high-ranking memory and a low-ranking memory, wherein the high-ranking memory and the low-ranking memory are electrically connected to the memory manager. The memory manager replaces information provided by the high-ranking memory with information provided by the low-ranking memory when a swap request is received.
    Type: Application
    Filed: March 29, 2019
    Publication date: June 25, 2020
    Inventors: CHIH-WEI SHEN, TING-SHUO HSU
  • Publication number: 20200187378
    Abstract: A server chassis includes a housing and two support portions. A bottom plate of the housing includes a loading surface and a three-dimensional reinforcing pattern integrally formed on the loading surface for reinforcing the structural strength of the bottom plate. The support portions are respectively located on an outer surface of the sidewall of the housing. A coverage area of the three-dimensional reinforcing pattern is greater than 10% of the total area of the loading surface. The three-dimensional reinforcing pattern includes a plurality of texture patterns regularly reproduced on the loading surface toward a linear axial direction. A maximum height of each of the texture patterns is 0.5-0.8 mm.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 11, 2020
    Inventors: Kuang-Yun SHEN, Cheng-Feng YANG, Chih-Wei HOU
  • Publication number: 20200177224
    Abstract: An electronic device base includes an upper case, a lower case, a base, a first hook component and a second hook component, a solenoid valve assembly, and a near field communication assembly. The upper case has an electronic device accommodation slot; the lower case is assembled to the upper case; the base is disposed between the upper and lower cases; the first and the second hook components are both disposed at the base. When the electronic device is placed into the electronic device accommodation slot, the first and the second hook components are forced by the electronic device to move along a first direction and a second direction, respectively, so the second hook component restricts the first hook component. The near field communication component is capable of communicating with an unlocking component and driving the solenoid valve assembly to actuate the second hook component to release the first hook component.
    Type: Application
    Filed: August 19, 2019
    Publication date: June 4, 2020
    Applicant: PEGATRON CORPORATION
    Inventors: HSIN-WEI SHEN, Chih-Cheng Hsu, Chun-Ho Huang
  • Patent number: 10658184
    Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
  • Publication number: 20200152666
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Patent number: 10640372
    Abstract: A method for fabricating a semiconductor device is disclosed. A semiconductor substrate comprising a MOS transistor is provided. A MEMS device is formed over the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: May 5, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • Patent number: 10642148
    Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Yu, Chi-Lun Lu, Chih-Tsung Shih, Ching-Wei Shen, Jeng-Horng Chen
  • Publication number: 20200077088
    Abstract: Method and apparatus of video coding using decoder derived motion information based on bilateral matching or template matching are disclosed. According to one method, an initial motion vector (MV) index is signalled in a video bitstream at an encoder side or determined from the video bitstream at a decoder side. A selected MV is then derived using bilateral matching, template matching or both to refine an initial MV associated with the initial MV index. In another method, when both MVs for list 0 and list 1 exist in template matching, the smallest-cost MV between the two MVs may be used for uni-prediction template matching if the cost is lower than the bi-prediction template matching. According to yet another method, the refinement of the MV search is dependent on the block size. According to yet another method, merge candidate MV pair is always used for bilateral matching or template matching.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Applicant: MEDIATEK INC.
    Inventors: Tzu-Der Chuang, Ching-Yeh Chen, Chih-Wei Hsu, Yu-Wen Huang, Jian-Liang Lin, Yu-Chen Sun, Yi-Ting Shen
  • Patent number: 10573635
    Abstract: A transient voltage suppression device with improved electrostatic discharge (ESD) robustness includes a semiconductor substrate having a first conductivity type, a first doped well having a second conductivity type, a first heavily-doped area having the first conductivity type, a second doped well having the second conductivity type, a second heavily-doped area having the first conductivity type, and a first current blocking structure. The first doped well is arranged in the semiconductor substrate. The first heavily-doped area is arranged in the first doped well. The second doped well is arranged in the semiconductor substrate. The second heavily-doped area is arranged in the second doped well. The first current blocking structure is arranged in the semiconductor substrate, spaced from the bottom of the semiconductor substrate, and arranged between the first doped well and the second doped well.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: February 25, 2020
    Assignee: Amazing Microelectronics Corp.
    Inventors: Chih-Wei Chen, Yu-Shu Shen, Kun-Hsien Lin
  • Publication number: 20200027873
    Abstract: A transient voltage suppression device with improved electrostatic discharge (ESD) robustness includes a semiconductor substrate having a first conductivity type, a first doped well having a second conductivity type, a first heavily-doped area having the first conductivity type, a second doped well having the second conductivity type, a second heavily-doped area having the first conductivity type, and a first current blocking structure. The first doped well is arranged in the semiconductor substrate. The first heavily-doped area is arranged in the first doped well. The second doped well is arranged in the semiconductor substrate. The second heavily-doped area is arranged in the second doped well. The first current blocking structure is arranged in the semiconductor substrate, spaced from the bottom of the semiconductor substrate, and arranged between the first doped well and the second doped well.
    Type: Application
    Filed: July 23, 2018
    Publication date: January 23, 2020
    Inventors: CHIH-WEI CHEN, YU-SHU SHEN, KUN-HSIEN LIN
  • Patent number: 10535680
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Publication number: 20200012874
    Abstract: An electronic device is disclosed. The electronic device includes a wireless module configured to emit a first radar signal and receive a second radar signal, which is the first radar signal reflected by a user; a gravity sensor configured to sense a status of the electronic device to generate a sensing result; and a control unit coupled to the wireless module and the gravity sensor, and configured to control the wireless module to emit the first radar signal when the sensing result conforms to an emitting condition and determine a physiological status of the user according to the second radar signal received by the wireless module.
    Type: Application
    Filed: October 11, 2018
    Publication date: January 9, 2020
    Inventors: Chih-Teng Shen, Cheng-Wei Chang
  • Patent number: 10529438
    Abstract: The present disclosure provides a dynamic random access device (DRAM). The DRAM includes a first node, a second node and a pad. The first node is configured to conduct a first internal signal generated by internal devices of the DRAM. The second node is configured to conduct a second internal signal generated by other internal devices of the DRAM. The pad is configured to receive one of the first internal signal and the second internal signal.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: January 7, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Wei Shen