Patents by Inventor Chih-Wei SUNG

Chih-Wei SUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369430
    Abstract: A method includes sequentially depositing a floating gate layer, a dielectric structure stack, and a control gate layer over a substrate. A first etching process is performed to pattern the control gate layer, the dielectric structure stack, and a top portion of the floating gate layer to form a control gate, a dielectric structure, and a top portion of a floating gate over a bottom portion of the floating gate layer. A sidewall of the top portion of the floating gate is concave. A first spacer structure is formed on the sidewall of the top portion of the floating gate, a sidewall of the dielectric structure, and a sidewall of the control gate. A second etching process is performed to pattern the bottom portion of the floating gate layer to form a bottom portion of the floating gate after forming the first spacer structure.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu LIN, Chi-Chung JEN, Chia-Ming PAN, Su-Yu YEH, Keng-Ying LIAO, Chih-Wei SUNG
  • Patent number: 11804529
    Abstract: A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Chia-Ming Pan, Su-Yu Yeh, Keng-Ying Liao, Chih-Wei Sung
  • Patent number: 11764229
    Abstract: A pixel array substrate, including a substrate, multiple conductors, a pixel driving circuit, a first pad, and a second pad, is provided. The substrate has a first surface, a second surface, and multiple through holes. The through holes extend from the first surface to the second surface. The conductors are respectively disposed in the through holes. The pixel driving circuit is disposed on the first surface of the substrate. The first pad and the second pad are disposed on the second surface of the substrate. The conductors include a first conductor, a second conductor, and a first dummy conductor. The first conductor is electrically connected to the pixel driving circuit and the first pad. The second conductor is electrically connected to the pixel driving circuit and the second pad. The first dummy conductor is overlapped with and electrically isolated from the pixel driving circuit.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: September 19, 2023
    Assignee: Au Optronics Corporation
    Inventors: Hsiu-Chun Hsieh, Hsin-Hung Sung, Shu-Hui Huang, Chih-Chung Su, Yi-Wei Chen, Fang-Hui Chan
  • Patent number: 11735668
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
  • Publication number: 20230262792
    Abstract: There is provided a wireless device including an earphone set and a charging cradle. The charging cradle is used as means for charging the earphone set. The charging cradle further records connection information of multiple external devices that have been BT connected to the charging cradle. The earphone set receives a connection command from the charging cradle to accordingly form an audio connection to one of the multiple external devices. The charging cradle is further used as a communication medium between the multiple external devices.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventors: Ping-Shun ZEUNG, Chih-Wei SUNG, Yu-Feng CHEN
  • Patent number: 11728170
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Ying Lin, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sheng-Yung Lo, C. W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Publication number: 20230253433
    Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Ying Liao, Yu-Chu Lin, Chih Wei Sung, Shih Sian Wang, Chi-Chung Jen, Yu-chien Ku, Yen-Jou Wu, Huai-jen Tung, Po-Zen Chen
  • Patent number: 11706271
    Abstract: A method utilized in a wireless device used to wirelessly receive and play audio information includes: receiving a data packet stream transmitted from an audio source; monitoring a data amount of at least one buffer of a memory of the wireless device; and tuning an audio clock frequency dedicated for playing audio samples if the data amount of the at least one buffer deviates from a specific data amount level.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: July 18, 2023
    Assignee: Airoha Technology Corp.
    Inventors: I-Ken Ho, Chih-Wei Sung, Wei-Chung Peng, Kuang-Hu Huang
  • Patent number: 11652133
    Abstract: In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer may be formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing CO.
    Inventors: H. L. Chen, Huai-jen Tung, Keng-Ying Liao, Po-Zen Chen, Su-Yu Yeh, Chih Wei Sung
  • Patent number: 11652127
    Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, S. S. Wang
  • Publication number: 20230062401
    Abstract: A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the first raised portion and in a region between the first raised portion and a second raised portion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on the second raised portion, a second polysilicon structure adjacent to the second raised portion and in the region between the first raised portion and the second raised portion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Ken-Ying LIAO, Chih-Wei SUNG, Tzu-Pin LIN, Huai-jen TUNG, Po-Zen CHEN, Yen-Jou WU, Yung-Lung YANG
  • Patent number: 11570605
    Abstract: There is provided an electronic device having Bluetooth communication function. The electronic device confirms whether a current packet received in a receive slot is a retransmitted packet according to a SEQN bit in the packet header so as to determine whether to continuously turn on an RF receiver in the receive slot or early turn off the RF receiver to save power.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 31, 2023
    Assignee: Airoha Technology Corp.
    Inventors: Yu-Feng Chen, Chih-Wei Sung
  • Patent number: 11513765
    Abstract: There is provided a Bluetooth audio system including a gateway, a primary device and at least one slave device. The gateway and the primary device communicate Bluetooth packets therebetween based on the standard Bluetooth communication protocol. The at least one slave device accomplishes synchronization with the primary device using a user-defined Bluetooth communication protocol so as to listen or snoop the Bluetooth packets exchanged between the gateway and the primary device.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: November 29, 2022
    Assignee: AIROHA TECHNOLOGY CORP.
    Inventors: Kuang-Hu Huang, Jing-Syuan Jia, Chih-Wei Sung, Wei-Chung Peng
  • Publication number: 20220367559
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-Zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-Kai Tsao, Yung-Lung Yang
  • Patent number: 11502123
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Keng-Ying Liao, Huai-Jen Tung, Chih Wei Sung, Po-zen Chen, Yu-Chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-kai Tsao, Yung-Lung Yang
  • Publication number: 20220359606
    Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, S.S. Wang
  • Publication number: 20220359781
    Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
  • Patent number: 11471034
    Abstract: A method for distinguishing plaque and calculus is provided. The method is used in a device and includes the following steps: emitting, by a blue light-emitting diode, blue light to illuminate teeth in an oral cavity, wherein the blue light is used to generate autofluorescence of plaque and calculus on the teeth; sensing, by an image sensor, the autofluorescence of plaque and calculus; and distinguishing, by a processor, a plaque area and a calculus area on the teeth based on the autofluorescence.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: October 18, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Kai-Ju Cheng, Hsin-Lun Hsieh, Chin-Yuan Ting, Tsung-Hsin Lu, Huan-Tang Wu, Shao-Ang Chen, Yu-Hsun Chen, Jia-Chyi Wang, Chih-Wei Sung, Huan-Pin Shen
  • Patent number: 11430909
    Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
  • Publication number: 20220216315
    Abstract: A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.
    Type: Application
    Filed: March 18, 2022
    Publication date: July 7, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu LIN, Chi-Chung JEN, Chia-Ming PAN, Su-Yu YEH, Keng-Ying LIAO, Chih-Wei SUNG