Abstract: Fluidic systems, devices and methods are provided for separating and sequestering particles from a fluid flow within traps in a fluidic chip is provided. The fluidic platform is particularly suited for parallel live zebrafish embryo studies providing automated zebrafish embryo trapping and flow through culture as well as whole mount zebrafish antibody staining functions. The zebrafish on a chip testing platform uses a chaotic hydrodynamic trapping process to trap and retain zebrafish embryos in a consistent body orientation (i.e., head pointed inward) without any external adjustments. The system and apparatus can also be adapted to be a multifunctional concentration gradient generator (CGG) that can be used to automatically immobilize dechorionated zebrafish embryos and generate chemical gradients for acute fish embryo toxicity (FET) tests.

Abstract: A latch calibration system includes a latch, a clock circuit and a calibration circuit. Latch latches logic data from a data node in an internal node. Latch includes two transistors respectively coupled between data node and internal node. Clock circuit generates first and second clock control signals. Calibration circuit is coupled to clock circuit and latch, and includes two bootstrap circuits coupled to clock circuit respectively. First bootstrap circuit generates a third clock control signal according to first clock control signal, which is output to a gate of first transistor. a high level of third clock control signal is greater than that of first clock control signal. Second bootstrap circuit generates a fourth clock control signal according to the second clock control signal, which is output to a gate of second transistor. A low level of fourth clock control signal is less than that of second clock control signal.

Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.

Abstract: A food status recognition and display system and a food status recognition and display method are provided. The food status recognition and display system includes a camera and light source module, a processing module and a display interface. The camera and light source module faces a food storage environment. After the camera and light source module photographs at least one food item using the light beams in a visible light band, a near-infrared light band and a short-wave infrared light band, respective food photography results are obtained. The processing module receives the food photography results. After the food photography results are processed through an image recognition process, a vegetation index formula, a vegetation water content formula and a vegetation correlation analysis formula, at least one corresponding food status information is generated and then transmitted.

Abstract: An imaging lens module has an image surface and includes an optical lens assembly, a plurality of monomer structures and a cover member. The optical lens assembly is disposed on an object side of the image surface and defines an optical axis. The optical lens assembly includes a light-blocking element, which includes a light-blocking portion. The light-blocking portion is disposed closer to the optical axis than a portion of the light-blocking element other than the light-blocking portion thereto. The monomer structures are disposed on the object side of the image surface, and each of the monomer structures is extended along a direction parallel to the optical axis. The cover member is disposed on an object side of the optical lens assembly, and the optical axis passes through the cover member. The monomer structures are disposed on the light-blocking portion of the light-blocking element.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: A method of forming a semiconductor memory device includes: forming a stack structure on a substrate, the stack structure including a plurality of dielectric layers and a plurality of sacrificial layers alternatingly stacked in a Z direction substantially perpendicular to the substrate; forming a plurality of source/drain trenches in the stack structure; conformally forming a barrier layer in the source/drain trenches, and then filling the source/drain trenches with a plurality of sacrificial segments; forming a protection layer over the stack structure to cover the barrier layer and the sacrificial segments; removing the sacrificial layers of the stack structure to form a plurality of spaces among the dielectric layers; forming a plurality of conductive layers in the spaces; sequentially removing the protection layer, the sacrificial segments and the barrier layer; and forming a plurality of memory structures in the source/drain trenches.

Abstract: A method, computer system, and a computer program product for smart SDN is provided. The present invention may include recording and clustering a pod's behavior to generate a behavior transition model for the pod. The present invention may include watching a behavior of the pod and comparing the behavior to the generated behavior transition model. The present invention may include triggering a network policy change based on determining that the behavior of the pod is a misbehavior.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An optical device includes a range finding module. The range finding module includes a first light condenser unit, a light emitting unit and a light receiving unit. The first light condenser unit defines an optical axis and a hole disposed along the optical axis. The first light condenser unit, the light emitting unit and the light receiving unit are sequentially arranged along the optical axis. The light is emitted by the light emitting unit, passes through the hole, reaches an object, is reflected by the object, is converged by the first light condenser unit and is received by the light receiving unit to generate an electrical signal.

Abstract: A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.

Abstract: A 3D image sensing device includes a first camera lens, a second camera lens and a light source. A 3D image processing method for the 3D image sensing device includes the following steps. Firstly, a target is photographed by the first camera lens and the second camera lens, and the obtained images are processed in a stereo vision mode. Consequently, a first depth map is obtained. After the light source emits plural feature points to the target, the target is photographed by the first camera lens and the second camera lens, and the obtained images are processed in an active stereo vision mode. Consequently, a second depth map is obtained. The first depth map and the second depth map are synthesized as a synthesized depth map according to a synthetization strategy.

Abstract: An antenna module and a related network communication device are provided in this disclosure. A network communication device includes a circuit board, a network communication chip, an antenna, a signal line, and an antenna bracket. The network communication chip is disposed on the circuit board. The antenna bracket has a first antenna slot, a circuit board slot, a circuit board hook and an opposite supporting part. The first antenna slot is configured to carry the antenna. The circuit board hook and the opposite supporting part are respectively located on opposing first surface and second surface of the circuit board. The circuit board slot is located between the circuit board hook and the opposite supporting part to accommodate the circuit board. The circuit board hook is buckled to a first buckle hole of the circuit board.

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

Abstract: A transistor structure includes a substrate, a first well region, a second well region, a gate structure, a drift region, a first doped region, a second doped region, and a first isolation structure. The first well region and the second well region are located in the substrate and adjacent to each other. The gate structure is located on the substrate. The drift region is located in the second well region on one side of the gate structure. The first doped region and the second doped region are located in the substrate on two sides of the gate structure. The first doped region is located in the first well region. The second doped region is located in the drift region. The first isolation structure is located in the substrate between the gate structure and the second doped region. The first well region has a first portion lower than a bottom surface of the drift region. The second well region has a second portion lower than the bottom surface of the drift region.

Abstract: The present invention provides a method for preparing conductor material with large surface area, which comprises steps of: forming a block layer on the outer surface of a support precursor (for example, a conductive nanometer fiber) for producing a mixed precursor; rolling the mixed precursor to crack a portion of the outer surface of the block layer for producing a plurality of crack-gaps and exposing a portion of the outer surface of the support precursor from the plurality of crack-gaps; and adding a conductor material to the mixed precursor so that the conductor material contacts and is connected electrically to the support precursor via the plurality of crack-gaps for producing a conductor material with large surface area.

Abstract: A control device includes multi-stage control circuits. An i-th stage control circuit includes an input signal generator and an acknowledge signal generator. The input signal generator generates an i+1-th stage input signal according to a first inverted output signal and an i+1-th stage acknowledge signal. The acknowledge signal generator generates an i-th stage acknowledge signal according to an i-th stage delayed input signal and a second inverted output signal, wherein i is an integer larger than 1. Phases of the first inverted output signal and the second inverted output signal are opposite to a phase of an i-th stage output signal generated by an i-th stage pulse signal generator.