Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

Abstract: A pixel array substrate including a substrate and pixel units arranged in an array on the substrate is provided. Each pixel unit includes a TFT having a source, a gate, and a drain, a pixel electrode electrically connected to the drain, a common electrode, an insulation layer, and a test electrode. The pixel electrode is located between the common electrode and the substrate. The common electrode has slits that expose the pixel electrode. The insulation layer is located between the common electrode and the pixel electrode and has a contact hole exposing the pixel electrode. The test electrode and the common electrode belong to the same film layer, and the test electrode is separated from the common electrode. The contact hole is filled with the test electrode, and the test electrode is electrically connected to the drain. A display panel including the pixel array substrate is also provided.

Abstract: An active element and a fabricating method thereof are provided. The active element includes a gate, a gate insulating layer, a channel, a source and a drain. The gate is disposed on a substrate. The gate insulating layer is disposed on the substrate and covers the gate. The gate insulating layer is divided into a first region having uniform thickness and a second region having uniform thickness. The thickness of the gate insulating layer in the first region is different from the thickness of the gate insulating layer in the second region. The channel is disposed on the gate insulating layer. The source and the drain are disposed on the gate insulating layer and separated from each other. The distribution region of the source and the drain is identical to the distribution region of the first region. The channel contacts with the source and the drain.

Abstract: A gate driving circuit includes a first input terminal, a second input terminal, a third input terminal, an output terminal, a first transistor, a second transistor, a third transistor, and a capacitor. The first terminal of the first transistor is coupled to the first input terminal. The control terminal of the first transistor is coupled to the second input terminal. The first terminal of the second transistor is coupled to the third input terminal. The control terminal of the second transistor is coupled to the second terminal of the first transistor. The second terminal of the second transistor is coupled to the output terminal. The first terminal of the third transistor is coupled to the output terminal. The second terminal of the third transistor is coupled to ground terminal. The capacitor is coupled between the control terminal of the second transistor and the output terminal.

Abstract: A display panel includes a plurality of rows of pixels, a gate driving circuit, and an inspection circuit. The gate driving circuit includes a plurality of gate driving units. The inspection circuit includes a plurality of transistors. Each transistor includes a first terminal, a control terminal, and a second terminal. The first terminal of the transistor is coupled to a contact pad. The control terminal of the transistor is coupled to the corresponding gate driving unit and a corresponding row of pixels. The second terminal of the transistor is coupled to the control terminal of the transistor.

Abstract: A display panel includes a plurality of rows of pixels, a gate driving circuit, and an inspection circuit. The gate driving circuit includes a plurality of gate driving units. The inspection circuit includes a plurality of transistors. Each transistor includes a first terminal, a control terminal, and a second terminal. The first terminal of the transistor is coupled to a contact pad. The control terminal of the transistor is coupled to the corresponding gate driving unit and a corresponding row of pixels. The second terminal of the transistor is coupled to the control terminal of the transistor.

Abstract: A pixel array substrate including a substrate and pixel units arranged in an array on the substrate is provided. Each pixel unit includes a TFT having a source, a gate, and a drain, a pixel electrode electrically connected to the drain, a common electrode, an insulation layer, and a test electrode. The pixel electrode is located between the common electrode and the substrate. The common electrode has slits that expose the pixel electrode. The insulation layer is located between the common electrode and the pixel electrode and has a contact hole exposing the pixel electrode. The test electrode and the common electrode belong to the same film layer, and the test electrode is separated from the common electrode. The contact hole is filled with the test electrode, and the test electrode is electrically connected to the drain. A display panel including the pixel array substrate is also provided.

Abstract: A gate driving circuit includes a first input terminal, a second input terminal, a third input terminal, an output terminal, a first transistor, a second transistor, a third transistor, and a capacitor. The first terminal of the first transistor is coupled to the first input terminal. The control terminal of the first transistor is coupled to the second input terminal. The first terminal of the second transistor is coupled to the third input terminal. The control terminal of the second transistor is coupled to the second terminal of the first transistor. The second terminal of the second transistor is coupled to the output terminal. The first terminal of the third transistor is coupled to the output terminal. The second terminal of the third transistor is coupled to ground terminal. The capacitor is coupled between the control terminal of the second transistor and the output terminal.

Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.