Abstract: A method includes forming a first portion of a spacer layer over a first fin and a second portion of the spacer layer over a second fin, performing a first etching process to recess the first portion of the spacer layer with respect to the second portion of the spacer layer to form first spacers on sidewalls of the first fin, subsequently performing a second etching process to recess the second portion of the spacer layer with respect to the first spacers to form second spacers on sidewalls of the second fin, where the second spacers are formed to a height greater than that of the first spacers, and forming a first epitaxial source/drain feature and a second epitaxial source/drain feature between the first spacers and the second spacers, respectively, where the first epitaxial source/drain feature is larger than that of the second epitaxial source/drain feature.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: Embodiments of the present disclosure relates to a method for forming a semiconductor device structure. The method includes including forming one or more conductive features in a first interlayer dielectric (ILD), forming an etch stop layer on the first ILD, forming a second ILD over the etch stop layer, forming one or more openings through the second ILD and the etch stop layer to expose a top surface of the one or more first conductive features, wherein the one or more openings are formed by a first etch process in a first process chamber, exposing the one or more openings to a second etch process in a second process chamber so that the shape of the or more openings is elongated, and filling the one or more openings with a conductive material.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

Abstract: A method for managing a genuine fabric with blockchain data comprises the following steps: receiving at least one image of a genuine fabric photographed by a computing device, wherein the image contains at least one anti-counterfeiting texture generated during a manufacturing process thereof, and the computing device performs image analysis on the anti-counterfeiting texture to obtain at least one hash value; forming an smart contract with a text serial number corresponding to the genuine fabric and the hash value by one of a plurality of nodes in a blockchain through the computing device, and launching the smart contract to the nodes; and providing a key to at least one of a fabric production end and a brand sales end, wherein after the smart contract is signed, a non-fungible token which is associated with the genuine fabric is minted at one of the nodes in the blockchain.

Abstract: A method for forming an anti-counterfeiting feature during knitting of a fabric and a fabric thereof, the fabric is knitted with at least one first yarn, a part of the fabric includes a plurality of featured yarn loops formed by a second yarn, the featured yarn loops constitute an anti-counterfeiting feature, the anti-counterfeiting feature can be directly observed from one side surface of the fabric, the second yarn is formed by twisting at least two sub-yarns with different shades, and shades of the at least two sub-yarns and the first yarn are different from each other, and a shade of the featured yarn loops displayed on the side surface is random. Accordingly, the randomness of yarn twisting makes the anti-counterfeiting feature difficult to be replicated, thereby preventing unscrupulous manufacturers from counterfeiting the fabric.

Abstract: The invention provides a system for performing dynamic production and knitting machine work management comprising a production demand management unit, an advanced scheduling management unit, a cloth pattern storage unit and a manufacturing execution unit. The production demand management unit receives at least one production demand data. The advanced scheduling management unit generates a production scheduling data according to working conditions of a plurality of knitting machines and the production demand data. The cloth pattern storage unit stores a plurality of knitting machine work setting data. The manufacturing execution unit controls each knitting machine to extract one of the plurality of knitting machine work setting data from the cloth pattern storage unit based on a production cloth pattern data. The knitting machine work setting data is forcibly deleted by the knitting machine when a knitting number meets a set value defined by the knitting number limiting data.

Abstract: The present invention provides a method for verifying a product authenticity with fabric features, comprising steps of receiving at least one fabric partial image and performing image analysis to determine an image optical feature distribution information of an anti-counterfeiting feature, receiving a fabric serial number generated by operation of an input device, and determining whether a fabric is an authorized product by using the fabric serial number or the information.

Abstract: A method for forming an anti-counterfeiting feature during knitting of a fabric and a fabric thereof, the fabric is knitted with at least one first yarn, a part of the fabric includes a plurality of featured yarn loops formed by a second yarn, the featured yarn loops constitute an anti-counterfeiting feature, the anti-counterfeiting feature can be directly observed from one side surface of the fabric, the second yarn is formed by twisting at least two sub-yarns with different colours, and colours of the at least two sub-yarns and the first yarn are different from each other, and a colour of the featured yarn loops displayed on the side surface is random. Accordingly, the randomness of yarn twisting makes the anti-counterfeiting feature difficult to be replicated, thereby preventing unscrupulous manufacturers from counterfeiting the fabric.

Abstract: The invention provides a system for performing production and factory area material transportation management, comprising a production demand management unit, a warehouse management unit, an advanced scheduling management unit, a manufacturing execution unit and a transport dispatching unit. The production demand management unit receives at least one production demand data input externally. The warehouse management unit records a plurality of production material storage data. The advanced scheduling management unit outputs at least one production scheduling data based on the at least one production demand data and working states of a plurality of operation areas. The manufacturing execution unit generates at least one production execution data based on the production scheduling data.

Abstract: The invention provides a system for performing dynamic production and knitting machine work management comprising a production demand management unit, an advanced scheduling management unit, a cloth pattern storage unit and a manufacturing execution unit. The production demand management unit receives at least one production demand data. The advanced scheduling management unit generates a production scheduling data according to working conditions of a plurality of knitting machines and the production demand data. The cloth pattern storage unit stores a plurality of knitting machine work setting data. The manufacturing execution unit controls each knitting machine to extract one of the plurality of knitting machine work setting data from the cloth pattern storage unit based on a production cloth pattern data. The knitting machine work setting data is forcibly deleted by the knitting machine when a knitting number meets a set value defined by the knitting number limiting data.

Abstract: A vessel-shaped flute has a body and a captive cap. The cap is pivotally attached to the body with a pivot pin. A through hole is defined through the pivot pin. Consequently, the cap can cover the mouthpiece and all of the finger holes when the vessel-shaped flute is not in use. Protection is provided to the mouthpiece and finger holes to prevent them from being damaged or getting dirty. In addition, a cord can be threaded through the through hole. The user can wear the vessel-shaped flute as a necklace. The use and the decorative effect of the vessel-shaped flute are improved.