Patents by Inventor Chih Wen Lu
Chih Wen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250118656Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first conductive line, a first conductive via, a second conductive line, and a first barrier layer. The first conductive line is disposed on the substrate. The first conductive via is disposed on the first conductive line. The second conductive line is disposed on the first conductive line. The first barrier layer is disposed between the first conductive via and the second conductive line.Type: ApplicationFiled: October 6, 2023Publication date: April 10, 2025Inventors: HWEI-JAY CHU, HSI-WEN TIEN, WEI-HAO LIAO, YU-TENG DAI, HSIN-CHIEH YAO, CHENG-HAO CHEN, CHIH WEI LU
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Publication number: 20250110307Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: ApplicationFiled: December 12, 2024Publication date: April 3, 2025Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
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Publication number: 20250112087Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.Type: ApplicationFiled: October 3, 2023Publication date: April 3, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Tzu-Hui WEI, Chih Wei LU, Chan-Yu LIAO, Li-Ling SU, Chia-Wei SU, Yung-Hsu WU, Hsin-Ping CHEN
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Patent number: 12266565Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.Type: GrantFiled: June 30, 2022Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue, Yu-Teng Dai, Wei-Hao Liao
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Patent number: 12266594Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.Type: GrantFiled: November 22, 2023Date of Patent: April 1, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Yu Lai, Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang, Ching-Wei Tsai, Shang-Wen Chang
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Patent number: 12243775Abstract: In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.Type: GrantFiled: January 27, 2023Date of Patent: March 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee
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Publication number: 20250062195Abstract: A device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. The device further includes a first via in electrical contact with the power rail. The device further includes a first contact in electrical contact with the first via. The device further includes a first transistor in electrical contact with the first contact. The device further includes a second transistor in electrical isolation with the first transistor. The device further includes a second contact in electrical contact with the second transistor. The device further includes a second via in electrical contact with the second contact. The device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.Type: ApplicationFiled: November 5, 2024Publication date: February 20, 2025Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
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Patent number: 12218301Abstract: A manufacturing method of an electronic device includes: forming a conductive material layer on a substrate, the conductive material layer continuously extends from a first surface of the substrate to a second surface while passing through a side surface, wherein the side surface connects the first surface and the second surface, forming a first protection layer on the conductive material layer and patterning the conductive material layer by using the first protection layer as a mask to form an edge wire, wherein the edge wire is retracted relative to the first protection layer and forms an undercut structure, and forming a second protection layer on the substrate, wherein the second protection layer fills the undercut structure.Type: GrantFiled: January 16, 2024Date of Patent: February 4, 2025Assignee: AUO CorporationInventors: Chih-Wen Lu, Hao-An Chuang, Chun-Yueh Hou
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Patent number: 12204163Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: February 5, 2024Date of Patent: January 21, 2025Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20240154078Abstract: A manufacturing method of an electronic device includes: forming a conductive material layer on a substrate, the conductive material layer continuously extends from a first surface of the substrate to a second surface while passing through a side surface, wherein the side surface connects the first surface and the second surface, forming a first protection layer on the conductive material layer and patterning the conductive material layer by using the first protection layer as a mask to form an edge wire, wherein the edge wire is retracted relative to the first protection layer and forms an undercut structure, and forming a second protection layer on the substrate, wherein the second protection layer fills the undercut structure.Type: ApplicationFiled: January 16, 2024Publication date: May 9, 2024Applicant: AUO CorporationInventors: Chih-Wen Lu, Hao-An Chuang, Chun-Yueh Hou
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Publication number: 20240147639Abstract: An electronic device includes a substrate, a side wiring, a protective film, and a first filler. The substrate has a first surface, a second surface, and a side surface connected between the first surface and the second surface. The side wiring is disposed on the substrate and extends from the first surface to the second surface through the side surface. The protective film is disposed on the side wiring. The side wiring is sandwiched between the substrate and the protective film. An edge of the protective film extends beyond a side wall of the side wiring, and the protective film, the side wall of the side wiring, and the substrate define a gap. The first filler is disposed on the protective film and in the gap, wherein the first filler includes a first material and a plurality of particles mixed within the first material.Type: ApplicationFiled: October 4, 2023Publication date: May 2, 2024Applicant: AUO CorporationInventors: Chih-Wen Lu, Fan-Yu Chen, Chun-Yueh Hou, Hsi-Hung Chen
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Patent number: 11963300Abstract: A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.Type: GrantFiled: July 9, 2021Date of Patent: April 16, 2024Assignee: Au Optronics CorporationInventors: Chun-Yueh Hou, Hao-An Chuang, Fan-Yu Chen, Hsi-Hung Chen, Yun Cheng, Wen-Chang Hsieh, Chih-Wen Lu
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Patent number: 11923491Abstract: An electronic device, including a substrate, an edge wire, a first protection layer, and a second protection layer, is provided. The substrate has a first surface, a second surface, and a side surface connecting the first surface and the second surface. A normal vector of the side surface is different from the first surface and the second surface. The edge wire is configured on the substrate, extending from the first surface to the second surface while passing through the side surface. The first protection layer is configured on the edge wire. The edge wire is sandwiched between the substrate and the first protection layer. The edge wire and the first protection layer form an undercut structure. The second protection layer is configured on the substrate and fills the undercut structure. A manufacturing method of an electronic device is also provided.Type: GrantFiled: July 15, 2021Date of Patent: March 5, 2024Assignee: Au Optronics CorporationInventors: Chih-Wen Lu, Hao-An Chuang, Chun-Yueh Hou
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Publication number: 20230369372Abstract: A driver chip is provided. The driver chip includes a light-emitting module and a wafer substrate. The light-emitting module has multiple pins. The wafer substrate has a first surface and a second surface. The wafer substrate includes a photodiode, an image sensing circuit, and a light-emitting driving circuit. The photodiode is disposed on the second surface of the wafer substrate. The image sensing circuit is disposed in the wafer substrate and is electrically connected to the photodiode to drive the photodiode. The light-emitting driving circuit is disposed in the wafer substrate, and is electrically connected to the multiple pins of the light-emitting module via multiple connection units on the first surface of the wafer substrate to drive the light-emitting module.Type: ApplicationFiled: April 24, 2023Publication date: November 16, 2023Applicant: Yinscorp Ltd.Inventors: Ping-Hung Yin, Chih-Wen Lu, Jia-Shyang Wang, Jai-Jyun Shen
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Publication number: 20230237973Abstract: A high-speed buffer amplifier includes an input stage including a first channel coupled to receive differential inputs and a second channel coupled to receive the differential inputs; a middle stage including a first current source coupled to receive outputs of the second channel and electrically connected to power, a second current source coupled to receive outputs of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source; and an output stage coupled to the middle stage to generate an output voltage. A shunt circuit is electrically connected between the first current source and the second current source, and configured to bypass the floating current source.Type: ApplicationFiled: January 26, 2022Publication date: July 27, 2023Inventor: Chih-Wen Lu
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Patent number: 11705084Abstract: A high-speed buffer amplifier includes an input stage including a first channel coupled to receive differential inputs and a second channel coupled to receive the differential inputs; a middle stage including a first current source coupled to receive outputs of the second channel and electrically connected to power, a second current source coupled to receive outputs of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source; and an output stage coupled to the middle stage to generate an output voltage. A shunt circuit is electrically connected between the first current source and the second current source, and configured to bypass the floating current source.Type: GrantFiled: January 26, 2022Date of Patent: July 18, 2023Assignee: Himax Technologies LimitedInventor: Chih-Wen Lu
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Publication number: 20220052241Abstract: An electronic device, including a substrate, an edge wire, a first protection layer, and a second protection layer, is provided. The substrate has a first surface, a second surface, and a side surface connecting the first surface and the second surface. A normal vector of the side surface is different from the first surface and the second surface. The edge wire is configured on the substrate, extending from the first surface to the second surface while passing through the side surface. The first protection layer is configured on the edge wire. The edge wire is sandwiched between the substrate and the first protection layer. The edge wire and the first protection layer form an undercut structure. The second protection layer is configured on the substrate and fills the undercut structure. A manufacturing method of an electronic device is also provided.Type: ApplicationFiled: July 15, 2021Publication date: February 17, 2022Applicant: Au Optronics CorporationInventors: Chih-Wen Lu, Hao-An Chuang, Chun-Yueh Hou
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Publication number: 20220053638Abstract: A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.Type: ApplicationFiled: July 9, 2021Publication date: February 17, 2022Applicant: Au Optronics CorporationInventors: Chun-Yueh Hou, Hao-An Chuang, Fan-Yu Chen, Hsi-Hung Chen, Yun Cheng, Wen-Chang Hsieh, Chih-Wen Lu
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Patent number: 11196397Abstract: The present invention includes a current integrator for an organic light-emitting diode (OLED) panel. The current integrator includes an operational amplifier, which includes an output stage. The output stage, coupled to an output terminal of the current integrator, includes a first output transistor, a second output transistor, a first stack transistor and a second stack transistor. The first stack transistor is coupled between the first output transistor and the output terminal. The second stack transistor is coupled between the second output transistor and the output terminal.Type: GrantFiled: December 31, 2019Date of Patent: December 7, 2021Assignee: NOVATEK Microelectronics Corp.Inventors: Chih-Wen Lu, Chieh-An Lin, Yen-Ru Kuo, Jhih-Siou Cheng, Ju-Lin Huang
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Publication number: 20210286209Abstract: A display device includes a substrate, multiple spacers, multiple conductive particles, and a colloid layer. The spacers are disposed on the substrate. Each spacer has a first end closer to the substrate and a second end farther from the substrate, in which a width of the spacer is tapered from the first end to the second end. The conductive particles are disposed between the spacers. The colloid layer is disposed on the conductive particles and the spacers. A mother board is also disclosed.Type: ApplicationFiled: October 8, 2020Publication date: September 16, 2021Inventors: Chih-Wen LU, Yun-Ru CHENG, Kuan-Yi LEE