Abstract: A non-volatile memory stack provides high bandwidth support to a specialized processor such as an AI processor. The high bandwidth flash (HBF) stack may be unitary, including all non-volatile memory together with a memory controller, or it may be hybrid, including a mixture of non-volatile and volatile memory together with a controller. The processor may be mounted on an interposer, and one or more of the HBF stacks and/or hybrid HBF stacks may then be mounted on the interposer alongside the processor.

Abstract: The disclosure provides an animal cell stably expressing a virus-like particle (VLP). The disclosure also provides a method for manufacturing a virus-like particle, a virus-like particle, a vaccine composition, a method for preventing viral infection, and a method for producing antibodies.

Abstract: A high capacity, high bandwidth non-volatile memory device includes a number of vertically stacked semiconductor dies. Each semiconductor die includes one or more non-volatile storage structures. Through silicon vias (TSVs) are arranged in a pattern on each semiconductor die and are used to route signals lines that directly and independently connect one or more non-volatile storage structures on one or more semiconductor dies to a controller die of the high capacity, high bandwidth non-volatile memory device. Because signal lines and TSVs are used to directly connect each non-volatile storage structure directly to the controller die, the bandwidth capabilities of the high capacity, high bandwidth non-volatile memory device is increased when compared with current non-volatile memory devices.

Abstract: A method for performing block level exploration of integrated circuit (IC) design and associated electronic device and computer-readable medium are provided. The method may include running a synthesis control procedure on at least one processor within the electronic device, for performing automatic placement and routing of a target design of an IC.

Abstract: A wireless communication device includes an antenna module and a flexible substrate. The antenna module includes an antenna structure and a control chip. The control chip is configured to use an antenna structure to perform wireless communication. The flexible substrate is used to carry the antenna module and includes two substrate regions. The antenna structure includes a first antenna radiation plate and a second antenna radiation plate. An open slot is extended from an edge of the first antenna radiation plate to a center of the first antenna radiation plate. The second antenna radiation plate is disposed under the first antenna radiation plate to overlap the first antenna radiation plate. There is a distance between the first antenna radiation plate and the second antenna radiation plate, thus the second antenna radiation plate is coupled to the first antenna radiation plate.

Abstract: Methods for texturing a surface of a component which include partially submerging the component within a liquid such that a first portion of the component is not submerged in the liquid and a second portion of the component is submerged in the liquid; and contacting at least the first portion of the component with a laser beam at a power and for a period of time sufficient to texture the first portion of the component to a first surface roughness, wherein the second portion of the component is either not textured by the laser beam, or is textured to a lesser degree than the first portion of the component and has a second surface roughness which is less than the first surface roughness.

Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.

Abstract: An integrated nucleic acid processing apparatus includes a first operation area, a second operation area and a separation wall. The first operation area includes multiple carrying boards for placing objects and reagents for processing nucleic acids in samples, and multiple operation modules for performing operations of nucleic acid processing. The second operation area includes two extraction regions for respectively performing nucleic acid extractions. The separation wall separates the first operation area from the second operation area and includes two openable door sheets spatially corresponding to the two extraction regions. Nucleic acid extraction plates can be moved from the first operation area to the second operation area by means of the carrying boards as the two openable door sheets are opened, and be isolated in the second operation area for performing nucleic acid extractions as the two openable door sheets are closed.

Abstract: A signal conversion method includes transmitting an Ethernet packet from an Ethernet media access controller to a transceiver, stacking an Ethernet media access control protocol layer corresponding to the Ethernet packet to a wireless communication protocol layer by using a protocol stack for generating a wireless communication packet after the transceiver receives the Ethernet packet, and generating a wireless communication signal according to the wireless communication packet.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a gate structure and a first well region. The gate structure is disposed on the semiconductor substrate. The first well region having a first conductivity type is located in the semiconductor substrate. The first well region overlaps the gate structure. A first bottom of the first well region has a wave bottom surface.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first patterned structure on a memory region of a base structure and forming a second patterned structure and a third patterned structure on a logic region of the base structure, the first patterned structure including a first channel portion, the second patterned structure including a second channel portion, the third patterned structure including a third channel portion, each of the first, second and third channel portions having two exposed end surfaces which are opposite to each other; forming a patterned hard mask covering the first and third patterned structures; and performing an etching process through the patterned hard mask so as to reduce a minimum distance between the two exposed end surfaces of the second channel portion.

Abstract: An integrated circuit includes a metal/dielectric layer, a second dielectric layer, a bottom electrode, a resistance switch element, and a top electrode. The metal/dielectric layer has a first dielectric layer and a conductive feature in the first dielectric layer. The second dielectric layer is over the metal/dielectric layer. The bottom electrode is over and in contact with the conductive feature and surrounded by the second dielectric layer. The second dielectric layer has a tapered sidewall, a lower portion of the tapered sidewall of the second dielectric layer is covered by the bottom electrode, and an upper portion of the tapered sidewall of the second dielectric layer is free from coverage by the bottom electrode. The resistance switch element is over the bottom electrode. The top electrode is over the resistance switch element.

Abstract: A memory device and a method for controlling a verification voltage of a memory device are provided. The method includes: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector.

Abstract: A method includes forming a first stack of alternating first semiconductor layers and first sacrificial layers over a substrate; forming a second stack of alternating second semiconductor layers and second sacrificial layers over the first stack, wherein the first semiconductor layers and the second semiconductor layers are made of different materials; replacing the first sacrificial layers with third sacrificial layers; removing the second sacrificial layers, such that the second semiconductor layers are suspended over the substrate; after removing the second sacrificial layers, removing the third sacrificial layers, such that the first semiconductor layers are suspended over the substrate; forming a first metal gate structure wrapping around the first semiconductor layers; and forming a second metal gate structure wrapping around the second semiconductor layers.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a bottom transistor, and a top transistor above the bottom transistor. The bottom transistor includes a plurality of first nanostructures, a first source/drain feature adjoining the first nanostructures and a first gate stack wrapping the first nanostructures. The top transistor includes a plurality of second nanostructures, a second source/drain feature adjoining the second nanostructures and a second gate stack wrapping the second nanostructures, wherein a first thickness of the first nanostructures is different than a second thickness of the second nanostructures. The semiconductor structure further includes an interlayer dielectric layer interposing between the first source/drain feature and the second source/drain feature.

Abstract: An array antenna includes a flexible substrate formed by stacked liquid crystal polymer (LCP) layers and has at least one feed point. At least one serial antenna is arranged on the flexible substrate, and a microstrip is extended from the feed point to connect a plurality of radiating elements in series to form the serial antenna. The tail end one of the radiating elements of the serial antenna is connected to one end of a ground microstrip, and another end of the ground microstrip is short-circuited to the ground. The length of the ground microstrip is approximately one fourth of the wavelength of the center frequency of the array antenna. Feeding sections where microstrips feeding to the radiating elements are in a horn and/or groove shape. Desired frequency and bandwidth may be obtained by adjusting lengths and widths of feeding sections respectively.

Abstract: A blockchain-based room inventory management system includes a property management system (PMS) module and an intermediate server system. The PMS module may be under a hotel's direct control. The intermediate server system communicates with at least one online travel agency (OTA) module and/or at least one booking engine using Ethereum-based smart contracts for confirming and processing a room reservation event. If the room reservation event is confirmed to be a successful transaction, the intermediate server system also updates the successful transaction into the PMS module and a blockchain formed by multiple node servers. The blockchain contains multiple blocks arranged in a chronological order for distinguishing successful transactions of different moments. In this way, each successful transaction is prevented from wrongly preceded by a later successful transaction. And the room inventory management system neutralizes an overbooking issue accordingly.

Abstract: A probe head includes an upper pin holder and a lower pin holder coupled to the upper pin holder. A pin arrangement space is defined between the upper pin holder and the lower pin holder. A conductive film is disposed between the upper pin holder and the lower pin holder. A plurality of probe pins penetrates through the upper pin holder, the conductor film and the lower pin holder, and extends outwardly from a bottom surface of the lower pin holder.