Abstract: A method for performing block level exploration of integrated circuit (IC) design and associated electronic device and computer-readable medium are provided. The method may include running a synthesis control procedure on at least one processor within the electronic device, for performing automatic placement and routing of a target design of an IC.

Abstract: A wireless communication device includes an antenna module and a flexible substrate. The antenna module includes an antenna structure and a control chip. The control chip is configured to use an antenna structure to perform wireless communication. The flexible substrate is used to carry the antenna module and includes two substrate regions. The antenna structure includes a first antenna radiation plate and a second antenna radiation plate. An open slot is extended from an edge of the first antenna radiation plate to a center of the first antenna radiation plate. The second antenna radiation plate is disposed under the first antenna radiation plate to overlap the first antenna radiation plate. There is a distance between the first antenna radiation plate and the second antenna radiation plate, thus the second antenna radiation plate is coupled to the first antenna radiation plate.

Abstract: Methods for texturing a surface of a component which include partially submerging the component within a liquid such that a first portion of the component is not submerged in the liquid and a second portion of the component is submerged in the liquid; and contacting at least the first portion of the component with a laser beam at a power and for a period of time sufficient to texture the first portion of the component to a first surface roughness, wherein the second portion of the component is either not textured by the laser beam, or is textured to a lesser degree than the first portion of the component and has a second surface roughness which is less than the first surface roughness.

Abstract: A signal conversion method includes transmitting an Ethernet packet from an Ethernet media access controller to a transceiver, stacking an Ethernet media access control protocol layer corresponding to the Ethernet packet to a wireless communication protocol layer by using a protocol stack for generating a wireless communication packet after the transceiver receives the Ethernet packet, and generating a wireless communication signal according to the wireless communication packet.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a gate structure and a first well region. The gate structure is disposed on the semiconductor substrate. The first well region having a first conductivity type is located in the semiconductor substrate. The first well region overlaps the gate structure. A first bottom of the first well region has a wave bottom surface.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first patterned structure on a memory region of a base structure and forming a second patterned structure and a third patterned structure on a logic region of the base structure, the first patterned structure including a first channel portion, the second patterned structure including a second channel portion, the third patterned structure including a third channel portion, each of the first, second and third channel portions having two exposed end surfaces which are opposite to each other; forming a patterned hard mask covering the first and third patterned structures; and performing an etching process through the patterned hard mask so as to reduce a minimum distance between the two exposed end surfaces of the second channel portion.

Abstract: An integrated circuit includes a metal/dielectric layer, a second dielectric layer, a bottom electrode, a resistance switch element, and a top electrode. The metal/dielectric layer has a first dielectric layer and a conductive feature in the first dielectric layer. The second dielectric layer is over the metal/dielectric layer. The bottom electrode is over and in contact with the conductive feature and surrounded by the second dielectric layer. The second dielectric layer has a tapered sidewall, a lower portion of the tapered sidewall of the second dielectric layer is covered by the bottom electrode, and an upper portion of the tapered sidewall of the second dielectric layer is free from coverage by the bottom electrode. The resistance switch element is over the bottom electrode. The top electrode is over the resistance switch element.

Abstract: An array antenna includes a flexible substrate formed by stacked liquid crystal polymer (LCP) layers and has at least one feed point. At least one serial antenna is arranged on the flexible substrate, and a microstrip is extended from the feed point to connect a plurality of radiating elements in series to form the serial antenna. The tail end one of the radiating elements of the serial antenna is connected to one end of a ground microstrip, and another end of the ground microstrip is short-circuited to the ground. The length of the ground microstrip is approximately one fourth of the wavelength of the center frequency of the array antenna. Feeding sections where microstrips feeding to the radiating elements are in a horn and/or groove shape. Desired frequency and bandwidth may be obtained by adjusting lengths and widths of feeding sections respectively.

Abstract: A blockchain-based room inventory management system includes a property management system (PMS) module and an intermediate server system. The PMS module may be under a hotel's direct control. The intermediate server system communicates with at least one online travel agency (OTA) module and/or at least one booking engine using Ethereum-based smart contracts for confirming and processing a room reservation event. If the room reservation event is confirmed to be a successful transaction, the intermediate server system also updates the successful transaction into the PMS module and a blockchain formed by multiple node servers. The blockchain contains multiple blocks arranged in a chronological order for distinguishing successful transactions of different moments. In this way, each successful transaction is prevented from wrongly preceded by a later successful transaction. And the room inventory management system neutralizes an overbooking issue accordingly.

Abstract: A probe head includes an upper pin holder and a lower pin holder coupled to the upper pin holder. A pin arrangement space is defined between the upper pin holder and the lower pin holder. A conductive film is disposed between the upper pin holder and the lower pin holder. A plurality of probe pins penetrates through the upper pin holder, the conductor film and the lower pin holder, and extends outwardly from a bottom surface of the lower pin holder.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes first and second gates, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high-k layer and doped regions. The first and the second gates are disposed on a substrate. The dielectric hump is disposed on the substrate between the first gate and the second gate. The first spacer is disposed on a sidewall of the dielectric hump. The charge storage layer is disposed between the first gate and the substrate. The gate dielectric layer is disposed between the second gate and the substrate. The high-k layer is disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped regions are disposed in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: A light-emitting diode and a white light-emitting device are provided. The light-emitting diode includes a p-type semiconductor layer, an n-type semiconductor layer, and a light-emitting stacked layer disposed therebetween. The light-emitting stacked layer includes alternately-stacked well layers and barrier layers. The light-emitting stacked layer includes one or more second, third, fourth, and fifth well layers that have different indium concentrations, such that a C2 indium concentration, a C3 indium concentration, a C4 indium concentration, and a C5 indium concentration are respectively defined, and a relationship of the indium concentrations is C5>C4>C3>C2. The light-emitting stacked layer includes an n-side proximate section, a middle section, and a p-side proximate section along a thickness direction. The third well layer is disposed in the middle section, and the third well layer is disposed between the two second well layers.

Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.

Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin, the gate structure comprising: a first metallic layer; a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element; and an oxide layer between the first metallic layer and the second metallic layer.

Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.

Abstract: A power converter includes a high side switch, a low side switch, a low side driver, a loading detector, a configurable regulator and a high side driver. The low side driver generates a low side drive signal to control the low side switch. The configurable regulator generates a regulation voltage, a magnitude of which is greater when the loading detector detects that the power converter has light loading than when the loading detector detects that the power converter has heavy loading. The high side driver generates a high side drive signal that switches between the input voltage and the regulation voltage to control the high side switch.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: The transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer.