Abstract: Methods, systems, and devices for wireless communications are described. A transmitting device may transmit an expiration indication to a receiving device as part of a scheduling message for a transport block. The expiration indication may provide information related to an expiration time for the transport block. If the expiration time is reached prior to successful reception by a receiving device, the receiving device may assume that the transport block has expired and may refrain from transmitting a retransmission grant, or may empty a hybrid automatic repeat request (HARM) buffer associated with the transport block. If the transmitting device fails to successfully receive an indication from the receiving device of a successful reception of the transport block prior to the expiration period, the transmitting device may also assume that the transport block has expired.

Abstract: Methods, systems, and devices for wireless communication are described. In one example, a base station may dynamically configure a user equipment (UE) to monitor or avoid monitoring for a preemption indication. Accordingly, the UE may have a lower chance of monitoring for a preemption indication when it is unlikely that an uplink or downlink transmission will be preempted. In another example, a base station may transmit a control message indicating whether future indications received from the base station are to be interpreted as preemption indications or permission indications. Accordingly, the base station may choose to use either preemption indications or permission indications (e.g., based on the probability of collisions between mobile broadband (MBB) and low latency transmissions) to facilitate MBB and low latency communication multiplexing with limited signaling.

Abstract: A method of fabricating a semiconductor device includes applying a plasma to a portion of a metal dichalcogenide film. The metal dichalcogenide film includes a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A metal layer including a second metal is formed over the portion of the metal dichalcogenide film after applying the plasma.

Abstract: A semiconductor device includes a die stack having dies selected into the stack based on their thicknesses. After the dies are formed on a wafer and thinned, a metrology tool is used to determine the thicknesses of the dies in the wafer. These thicknesses are stored in a known thickness die (KTD) map, along with other information such as their standard and average deviations and their classification into a binning class. In one example, dies which have been classified into bin 1 (having an optimal thickness) are selected to provide a high capacity highly reliable semiconductor device. In a further example, dies of different bins are mixed and matched to provide a uniform, highly controlled overall die stack height.

Abstract: In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.

Abstract: In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.

Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. The semiconductor device may further include a CMOS logic circuit as part of the pair of semiconductor dies or in its own semiconductor die mounted to the pair of semiconductor dies.

Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. The semiconductor device may further include a CMOS logic circuit as part of the pair of semiconductor dies or in its own semiconductor die mounted to the pair of semiconductor dies.

Abstract: To reduce the edge roll off in a semiconductor wafering process, the wafer (110) is subject to a plasma etch with an edge underetch. The edge underetch is achieved by means of a wafer holder (410) that emits gas towards the wafer (e.g. a gas vortex) to draw the wafer towards the holder's body (460). The plasma impinges on the wafer surface (110.1) opposite to the body. Some of the gas emitted by the holder wraps around the wafer edge and dilutes the etchant near the wafer edge. Consequently, the etch proceeds slower near the edge (the edge is underetched). In some embodiments, the wafer is rotated around an axis (440) passing through the wafer to increase the underetch.