Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Abstract: A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.

Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Abstract: A method for static power characterization of an analog integrated circuit includes detecting whether each of a plurality of input pins is electrically connected to a specific circuit; selecting a plurality of test benches of the static power characterization according to a number of the input pins electrically connected to the specific circuit; and processing the plurality of selected test benches of the static power characterization.

Abstract: A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.