Abstract: A semiconductor device includes a first and a second semiconductor fins extending along a first direction; an isolation region disposed between respective lower portions of the first and second semiconductor fins; a dielectric structure disposed between the first and the second semiconductor fins and above the isolation region, with a bottom surface aligned with a top surface of the isolation region; a gate isolation structure vertically disposed above the dielectric structure; and a metal gate layer extending along a second direction perpendicular to the first direction. The metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure separates the first and second portions of the metal gate layer from each other and includes a top portion vertically extending above the dielectric structure and a bottom portion extending into the dielectric structure.

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

Abstract: A display apparatus includes a driving backplane and a light emitting component. The driving backplane has a first pad and a second pad. The light emitting component is disposed on the driving backplane. The light emitting component includes a first semiconductor layer, a second semiconductor layer, an active layer, a first electrode, a second electrode, a first solder and a second solder. The first solder and the second solder of the light-emitting component are respectively disposed on the first pad and the second pad of the driving backplane and electrically connected to the first pad and the second pad respectively. A volume of the first solder is larger than a volume of the second solder, and an area of the first pad is smaller than an area of the second pad.

Abstract: A light emitting element substrate includes a substrate and a light emitting element disposed on the substrate and including first and second semiconductor layers, an active layer, first and second electrodes, and first and second solders. The second semiconductor layer is disposed opposite to the first semiconductor layer. The active layer is disposed between the first and second semiconductor layers. The first and second electrodes are electrically connected to the first and second semiconductor layers respectively. The first and second solders are respectively disposed on and electrically connected to the first and second electrodes respectively. The first electrode includes a first under barrier pattern. The first solder covers the first under barrier pattern. A projection area of the first solder on the substrate is greater than a projection area of the first under barrier pattern on the substrate. A display apparatus is provided.

Abstract: A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric structure disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric structure. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure separates the first and second portions of the metal gate layer from each other and includes a bottom portion extending into the dielectric structure.

Abstract: The present disclosure provides an artificial leather structure, comprising a woven layer, a porous elastomer layer disposed on the woven layer and a nonwoven layer disposed on the porous elastomer layer. The porous elastomer layer is adhered to the woven layer and the nonwoven layer.

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. one of the cells which is coupled to one of the first input pads and one of the second input pads is turned on, and a current flowing through the turned-on cell is measured.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

Abstract: A self-driven power generation module and a manufacturing method thereof are provided. The self-driven power generation module includes an upper structure, a lower structure, and a charge accumulation layer. The upper structure includes a first encapsulating layer, a first supporting layer, and a first electrode layer. The first supporting layer contacts the first encapsulating layer. The first electrode layer contacts the first supporting layer. The lower structure is spaced apart from the upper structure. The lower structure includes a second encapsulating layer, a second supporting layer, a second electrode layer, a third supporting layer, and a third electrode layer. The third supporting layer is disposed on the second encapsulating layer and spaced apart from the second supporting layer. The third electrode layer is disposed on the third supporting layer. The charge accumulation layer is disposed between the upper structure and the lower structure.

Abstract: The present disclosure relates to the fields of a method a kit for molecular diagnostics and genomics. More particularly, this disclosure relates to a method and a kit fir detecting a DNA fragment joining event or distinguishing an alternative splicing event. The present disclosure also relates to a method for administering a subject with proper treatment by steps of determining the risk of a particular cancer type or genotype.

Abstract: A intelligent long-distance infrared fill-light set for illuminating a predetermined target range at least 500 meters away cooperates with an infrared image-acquisition equipment to obtain an image of an illuminated-object, and includes: infrared fill-lights each including an optical lens, optical axis passing through a focus, infrared light sources emitting an infrared beam having a main beam angle, to generate a substantial overlapping area and at least one non-overlapping area when illuminating to the predetermined target range; enabling devices that enable light sources; and a control unit receiving image data acquired by the infrared image-acquisition equipment, for calculating and adjusting the enabling device to locally strengthen or weaken the substantial overlapping area and/or non-overlapping area.

Abstract: A intelligent long-distance infrared fill-light set for illuminating a predetermined target range at least 500 meters away cooperates with an infrared image-acquisition equipment to obtain an image of an illuminated-object, and includes: infrared fill-lights each including an optical lens, optical axis passing through a focus, infrared light sources emitting an infrared beam having a main beam angle, to generate a substantial overlapping area and at least one non-overlapping area when illuminating to the predetermined target range; enabling devices that enable light sources; and a control unit receiving image data acquired by the infrared image-acquisition equipment, for calculating and adjusting the enabling device to locally strengthen or weaken the substantial overlapping area and/or non-overlapping area.

Abstract: A method for repairing etching damage on a nitride-based epitaxial layer of an optoelectronic device and an optoelectronic device attributable thereto are provided. The method includes: providing a nitrogen-containing working liquid and a annealing apparatus having a reaction chamber; heating the reaction chamber to a predetermined temperature; atomizing the nitrogen-containing working liquid, and introducing the thus formed nitrogen-containing spray into the reaction chamber; and subjecting the optoelectronic device to an annealing treatment in the reaction chamber in the presence of the nitrogen-containing spray, so as to repair the etching damage on the nitride-based epitaxial layer.

Abstract: The present invention provides a composite intelligent biological phototherapy device including a base structure, a plurality of white light fluorescent tubes arranged side by side on the base structure, a plurality of LEDs disposed between the white light fluorescent tubes, a housing having an opening and configured to accommodate the base structure and the white light fluorescent tubes and the LEDs thereon, a light-transmittable plate disposed on the housing corresponding to the opening, and an control module configured to respectively control the white light fluorescent tubes and the LEDs. The base structure includes a plurality of sections, and each of the sections has a first surface facing the light-transmittable plate. The white light fluorescent tubes and the LEDs are provided on the first surfaces, and the sections are bent relative to each other so an angle between the first surfaces of adjacent sections is less than 180 degrees.