Abstract: A system and method for supporting multiple graphics processing units (GPUs) includes a first communication path coupled to a root complex device and a first connection point of a first GPU. A second communication path is coupled to the root complex device and a first set of switches. The first set of switches is configured to route communications between the root complex device to either a second connection point of the first GPU via a second set of switches or to a first connection point of a second GPU. The second set of switches is coupled to a second connection point of the first GPU. The second set of switches is configured to route communications to and from the second connection point of the first GPU and to either the root complex device via the first set of switches or to a second connection point of the second GPU.

Abstract: Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.

Abstract: Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.

Abstract: A fault tolerant graphics controller that generates error codes for graphics commands and checks the error codes before the graphics controller executes the command. The error code generator may be configured to detect and correct errors or to just detect errors. If an error is detected or an uncorrectable error occurs, the host computing system can be informed or interrupted, the erroneous command can be flushed from the graphics controller or the commands before and after the possibly erroneous command can be stored to help determine the erroneous command. Error codes can be generated on a block basis and stored in the frame buffer, thereby having minimal impact on system performance.

Abstract: A fault tolerant graphics controller that generates error codes for graphics commands and checks the error codes before the graphics controller executes the command. The error code generator may be configured to detect and correct errors or to just detect errors. If an error is detected or an uncorrectable error occurs, the host computing system can be informed or interrupted, the erroneous command can be flushed from the graphics controller or the commands before and after the possibly erroneous command can be stored to help determine the erroneous command. Error codes can be generated on a block basis and stored in the frame buffer, thereby having minimal impact on system performance.