Abstract: An optical module includes a base, a first optical component and at least two washers. The first optical component is disposed on the base and the first optical component has a flange. The washers are disposed on the first optical component and sandwiched in between the base and the flange. Each of the washers has a first side surface and a second side surface, wherein the first side surface and the second side surface tilt with respect to each other by an angle.

Abstract: The present invention is directed to a depot composition for sustained release delivery of buprenorphine with enhanced stability and bioavailability. The composition is an injectable, low viscosity liquid and can form a depot in situ capable of delivering therapeutic level of buprenorphine over a period of time from one week to 3 months.

Abstract: An optical module includes a housing, an optical component, a first elastic member and a second elastic member. The housing has a first end, a second end and a through hole, wherein the first end is opposite to the second end. The optical component is disposed in the through hole. The optical component has a third end and a fourth end, wherein the third end is opposite to the fourth end, the third end protrudes from the first end, and the fourth end protrudes from the second end. The first elastic member is rotatably disposed on the first end and abuts against the third end. The second elastic member is rotatably disposed on the second end and abuts against the fourth end.

Abstract: The disclosure provides a gate driving circuit on array applied to a display panel with charge sharing pixel structure. In particular, the gate driving circuit is adapted to receive multi-phase clock signal and includes a plurality of shift registers. Each shift register includes a driving circuit including a first driving transistor and a second driving transistor, a pull-down unit and at least one pull-up unit, so that is capable of generating mutually non-overlapped main gate driving signal and sub gate driving signal. Furthermore, the advantage of the disclosure is to provide a gate driving circuit with simplified circuit structure and circuit layout.

Abstract: A liquid crystal display device includes a plurality of pixel driving circuits and a pixel array. Each pixel driving circuit of the plurality of pixel driving circuits includes four thin film transistors and has four output terminals, where each thin film transistor is used for driving an output terminal of the four output terminals, and the four output terminals are coupled to two gate lines and two sharing lines respectively for outputting two main output signals and two sharing output signals. The phases and timings of the two main output signals and the two sharing output signals are all the same. A pixel of the pixel array is charged/discharged to a specific voltage level according to a main output signal of the two main output signals, a sharing output signal, and a signal of a data line.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A LCD panel with an improved pixel array configuration is provided. The LCD panel uses a column inversion driving method to drive the data lines so as to achieve a stable common voltage. Moreover, by cross-connecting the layout traces of the wiring zone in a specified manner, the gate pulses outputted from every two gate lines neighboring the sub-pixel are not overlapped with each other, so that the frame can be normally displayed.

Abstract: A shift register comprises a plurality of stages. In one embodiment, each stage includes a first output, a second output, a pull-up circuit electrically coupled between a node and the second output, a pull-up control circuit electrically coupled to the node, a pull-down control circuit electrically coupled between the node and the first output, and a control circuit electrically coupled to the node and the first output.

Abstract: A display device having bi-directional shift registers is disclosed. The display device includes a display panel, a first dummy shift register set, a second dummy shift register set, a third dummy shift register sets, a fourth dummy shift register sets, a first valid shift register set coupled between the first dummy shift register set and the second dummy shift register set, a second valid shift register set coupled between the third dummy shift register set and the fourth dummy shift register set, and a first directional circuit coupled to a first valid register in the first valid register set and the third dummy shift register set.

Abstract: A shift register circuit includes a plurality of shift registers. Each of the shift registers is configured for outputting a corresponding start-pulse signal and a corresponding driving-pulse signal. Each of the shift registers includes a pull-up circuit, a first driving circuit, a second driving circuit and a discharging circuit. The pull-up circuit is configured for charging a first node. The first driving circuit is configured for generating the corresponding start-pulse signal, and the second driving circuit is configured for generating the corresponding driving-pulse signal. The discharging circuit firstly discharges the first node before discharging an output terminal of the second driving circuit.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A liquid crystal display device includes a plurality of pixel driving circuits and a pixel array. Each pixel driving circuit of the plurality of pixel driving circuits includes four thin film transistors and has four output terminals, where each thin film transistor is used for driving an output terminal of the four output terminals, and the four output terminals are coupled to two gate lines and two sharing lines respectively for outputting two main output signals and two sharing output signals. The phases and timings of the two main output signals and the two sharing output signals are all the same. A pixel of the pixel array is charged/discharged to a specific voltage level according to a main output signal of the two main output signals, a sharing output signal, and a signal of a data line.

Abstract: The disclosure provides a gate driving circuit on array applied to a display panel with charge sharing pixel structure. In particular, the gate driving circuit is adapted to receive multi-phase clock signal and includes a plurality of shift registers. Each shift register includes a driving circuit including a first driving transistor and a second driving transistor, a pull-down unit and at least one pull-up unit, so that is capable of generating mutually non-overlapped main gate driving signal and sub gate driving signal. Furthermore, the advantage of the disclosure is to provide a gate driving circuit with simplified circuit structure and circuit layout.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A LCD panel with an improved pixel array configuration is provided. The LCD panel uses a column inversion driving method to drive the data lines so as to achieve a stable common voltage. Moreover, by cross-connecting the layout traces of the wiring zone in a specified manner, the gate pulses outputted from every two gate lines neighboring the sub-pixel are not overlapped with each other, so that the frame can be normally displayed.