Patents by Inventor Chih-Ying Lin

Chih-Ying Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190388340
    Abstract: Disclosed herein is an oral dosage formulation suitable for treating a neurodegenerative disorder. The oral dosage formulation contains both sustained-release and immediate-release drugs. The sustained-release drug in the oral dosage formulation is memantine, and the immediate-release drug in the oral dosage formulation is donepezil and/or memantine, and the formulation is characterized in having a pH-independent dissolution profile of memantine at a pH range from about 1.0 to about 7.0.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 26, 2019
    Applicants: Center Laboratories, Inc., Medical and Pharmaceutical Industry Technology and Development Center
    Inventors: Meng-Ju LEE, Shu-Hsien CHANG, Chih-Chiang YANG, Yuan-Chih LE, Tse-Ching LIN, Ko-Chiang CHEN, Lai-Cheng CHIN, Tai-Yin KE, Pei-Ying LIAO
  • Publication number: 20190378752
    Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.
    Type: Application
    Filed: June 16, 2019
    Publication date: December 12, 2019
    Inventors: Chi-Ying Hsieh, Chih-Jung Chen, Chien-Hung Chen, Chih-Yueh Li, Cheng-Pu Chiu, Shih-Min Lu, Yung-Sung Lin
  • Patent number: 10381228
    Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 13, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Ted Ming-Lang Guo, Chin-Cheng Chien, Chih-Chien Liu, Hsin-Kuo Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 10373861
    Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 6, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Ying Hsieh, Chih-Jung Chen, Chien-Hung Chen, Chih-Yueh Li, Cheng-Pu Chiu, Shih-Min Lu, Yung-Sung Lin
  • Publication number: 20190216368
    Abstract: A method of predicting daily living activities performance of a person with disabilities includes establishing a rehabilitation assessments panel based on a plurality of rehabilitation evaluation scales and laboratory data; evaluating a plurality of persons with disabilities by the rehabilitation assessments panel; entering assessment results and the corresponding activities of daily living (ADL) performance into a machine learning platform; utilizing variable selection methods to select a plurality of variables having optimal classification performance from the rehabilitation assessments panel; executing a machine learning algorithm to create an ADL prediction model based on the selected variables; evaluating a participant in terms of the rehabilitation assessments panel; and entering assessment results into the ADL prediction model for calculation, thereby obtaining a prediction result of future ADL performance for the participant.
    Type: Application
    Filed: January 13, 2018
    Publication date: July 18, 2019
    Applicants: CHANG GUNG MEMORIAL HOSPITAL, LINKOU, Chang Gung University
    Inventors: Chih-Kuang Chen, Chun-Hsien Chen, Hsin-Yao Wang, Wan-Ying Lin
  • Publication number: 20190173103
    Abstract: An electrode plate is provided, which includes a metal base with a flow channel structure disposed between rib portions. A graphite layer wraps the bottom of the flow channel structure, the sidewalls of the flow channel structure, and the rib portions. A hydrophobic layer is disposed on the graphite layer overlying the bottom and the sidewalls of the flow channel structure, and not on the graphite layer overlying the rib portions. The hydrophobic layer on the bottom of the flow channel structure and the hydrophobic layer on the sidewalls of the flow channel structure have a substantially equal thickness.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 6, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Cheng-Hong LIU, Ching-Ying HUANG, Chih-Chia LIN, Wen-Lin WANG
  • Patent number: 9087596
    Abstract: The disclosure provides a gate driving circuit on array applied to a display panel with charge sharing pixel structure. In particular, the gate driving circuit is adapted to receive multi-phase clock signal and includes a plurality of shift registers. Each shift register includes a driving circuit including a first driving transistor and a second driving transistor, a pull-down unit and at least one pull-up unit, so that is capable of generating mutually non-overlapped main gate driving signal and sub gate driving signal. Furthermore, the advantage of the disclosure is to provide a gate driving circuit with simplified circuit structure and circuit layout.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: July 21, 2015
    Assignee: AU OPTRONICS CORP.
    Inventors: Kuo-Chang Su, Yung-Chih Chen, Yu-Chung Yang, Chih-Ying Lin
  • Patent number: 8890790
    Abstract: A liquid crystal display device includes a plurality of pixel driving circuits and a pixel array. Each pixel driving circuit of the plurality of pixel driving circuits includes four thin film transistors and has four output terminals, where each thin film transistor is used for driving an output terminal of the four output terminals, and the four output terminals are coupled to two gate lines and two sharing lines respectively for outputting two main output signals and two sharing output signals. The phases and timings of the two main output signals and the two sharing output signals are all the same. A pixel of the pixel array is charged/discharged to a specific voltage level according to a main output signal of the two main output signals, a sharing output signal, and a signal of a data line.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: November 18, 2014
    Assignee: AU Optronics Corp.
    Inventors: Chih-Ying Lin, Chun-Hsin Liu, Kuo-Chang Su, Yung-Chih Chen
  • Patent number: 8774348
    Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: July 8, 2014
    Assignee: AU Optronics Corp.
    Inventors: Chih-Ying Lin, Kun-Yueh Lin, Yu-Chung Yang, Kuo-Hua Hsu
  • Patent number: 8723772
    Abstract: A LCD panel with an improved pixel array configuration is provided. The LCD panel uses a column inversion driving method to drive the data lines so as to achieve a stable common voltage. Moreover, by cross-connecting the layout traces of the wiring zone in a specified manner, the gate pulses outputted from every two gate lines neighboring the sub-pixel are not overlapped with each other, so that the frame can be normally displayed.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: May 13, 2014
    Assignee: AU Optronics Corp.
    Inventors: Yu-Chung Yang, Kuo-Chang Su, Yung-Chih Chen, Kuo-Hua Hsu, Chih-Ying Lin, Kun-Yueh Lin
  • Patent number: 8537094
    Abstract: A shift register comprises a plurality of stages. In one embodiment, each stage includes a first output, a second output, a pull-up circuit electrically coupled between a node and the second output, a pull-up control circuit electrically coupled to the node, a pull-down control circuit electrically coupled between the node and the first output, and a control circuit electrically coupled to the node and the first output.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: September 17, 2013
    Assignee: AU Optronics Corporation
    Inventors: Yu-Chung Yang, Yung-Chih Chen, Chih-Ying Lin, Kuo-Hua Hsu
  • Patent number: 8519935
    Abstract: A display device having bi-directional shift registers is disclosed. The display device includes a display panel, a first dummy shift register set, a second dummy shift register set, a third dummy shift register sets, a fourth dummy shift register sets, a first valid shift register set coupled between the first dummy shift register set and the second dummy shift register set, a second valid shift register set coupled between the third dummy shift register set and the fourth dummy shift register set, and a first directional circuit coupled to a first valid register in the first valid register set and the third dummy shift register set.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: August 27, 2013
    Assignee: AU Optronics Corp.
    Inventors: Yung-Chih Chen, Kuo-Chang Su, Chih-Ying Lin, Yu-Chung Yang
  • Patent number: 8515000
    Abstract: A shift register circuit includes a plurality of shift registers. Each of the shift registers is configured for outputting a corresponding start-pulse signal and a corresponding driving-pulse signal. Each of the shift registers includes a pull-up circuit, a first driving circuit, a second driving circuit and a discharging circuit. The pull-up circuit is configured for charging a first node. The first driving circuit is configured for generating the corresponding start-pulse signal, and the second driving circuit is configured for generating the corresponding driving-pulse signal. The discharging circuit firstly discharges the first node before discharging an output terminal of the second driving circuit.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: August 20, 2013
    Assignee: Au Optronics Corp.
    Inventors: Yu-Chung Yang, Yung-Chih Chen, Chih-Ying Lin, Kun-Yueh Lin
  • Patent number: 8363777
    Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 29, 2013
    Assignee: AU Optronics Corp.
    Inventors: Chih-Ying Lin, Kun-Yueh Lin, Yu-Chung Yang, Kuo-Hua Hsu
  • Publication number: 20120328070
    Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.
    Type: Application
    Filed: September 6, 2012
    Publication date: December 27, 2012
    Applicant: AU Optronics Corp.
    Inventors: Chih-Ying Lin, Kun-Yueh Lin, Yu-Chung Yang, Kuo-Hua Hsu
  • Patent number: 8331524
    Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: December 11, 2012
    Assignee: AU Optronics Corp.
    Inventors: Kuo-Hua Hsu, Chun-Hsin Liu, Yung-Chih Chen, Chih-Ying Lin, Kuo-Chang Su, Yu-Chung Yang
  • Patent number: 8284891
    Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: October 9, 2012
    Assignee: AU Optronics Corp.
    Inventors: Chih-Ying Lin, Kun-Yueh Lin, Yu-Chung Yang, Kuo-Hua Hsu
  • Publication number: 20120219105
    Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.
    Type: Application
    Filed: May 10, 2012
    Publication date: August 30, 2012
    Inventors: Chih-Ying Lin, Kun-Yueh Lin, Yu-Chung Yang, Kuo-Hua Hsu
  • Publication number: 20120169679
    Abstract: A liquid crystal display device includes a plurality of pixel driving circuits and a pixel array. Each pixel driving circuit of the plurality of pixel driving circuits includes four thin film transistors and has four output terminals, where each thin film transistor is used for driving an output terminal of the four output terminals, and the four output terminals are coupled to two gate lines and two sharing lines respectively for outputting two main output signals and two sharing output signals. The phases and timings of the two main output signals and the two sharing output signals are all the same. A pixel of the pixel array is charged/discharged to a specific voltage level according to a main output signal of the two main output signals, a sharing output signal, and a signal of a data line.
    Type: Application
    Filed: December 12, 2011
    Publication date: July 5, 2012
    Inventors: Chih-Ying Lin, Chun-Hsin Liu, Kuo-Chang Su, Yung-Chih Chen
  • Patent number: D803839
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: November 28, 2017
    Assignee: ZEROPLUS TECHNOLOGY CO., LTD.
    Inventor: Chih-Ying Lin