Patents by Inventor Chih YUAN
Chih YUAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250244252Abstract: The present disclosure discloses an inspection device and an inspection method. The inspection device includes a first light source, a second light source, a light source controller and a sensor. The light source controller is configured to enable the first light source to irradiate an object under inspection in a first period of an inspection phase, and to enable the second light source to irradiate the object under inspection in a second period of the inspection phase. The sensor continuously senses the reflected light of the object under inspection in an exposure period of the inspection phase so as to obtain image data of the object under inspection. The exposure period includes the first period and the second period.Type: ApplicationFiled: August 16, 2024Publication date: July 31, 2025Inventors: CHIH-YUAN LIN, CHIN-YU LIU, YU-WEI LIU, HUNG-CHUN LO, CHAO-YU HUANG, CHUN-PIN HSU, CHENG-TAO TSAI
-
Patent number: 12375948Abstract: Examples provide new roaming test systems for network deployments that can be implemented remotely using a single physical AP. Examples achieve this elegant system by emulating a physical network deployment using a group of VAPs provisioned on the single physical AP (a VAP may refer to a logical or a virtual AP instance on a physical AP). Each VAP of CAP group may be configured to represent a physical AP of the physical network deployment (such a network deployment may be a prospective deployment or, an actual/set-up deployment). Examples can simulate/emulate a wireless client physically moving between physical APs of the network deployment by varying transmission power associated with each VAP as a function of time in a manner that mirrors how a wireless client would perceive transmission power varying for physical APs of the network deployment (represented by the VAPs) as the wireless client moves across the geographical site of the network deployment.Type: GrantFiled: October 4, 2022Date of Patent: July 29, 2025Assignee: Hewlett Packard Enterprise Development LPInventors: Tejas Sathe, Amogh Guruprasad Deshmukh, Liang-Chih Yuan
-
Publication number: 20250232928Abstract: A switch device includes at least one switch module and at least one welding protective plate. The switch module includes an enclosure for receiving a plurality of control terminals and a driving member therein. The control terminals respectively have an end projected from an end or a rear side of the enclosure. The driving member is controllable to change an electrically connected or disconnected state between the control terminals. The welding protective plate is provided on the enclosure at the end from where the control terminals are projected. The projected control terminals further extend through the welding protective plate to be welded to a circuit board. The welding protective plate can withstand a high temperature and is located between the switch module and the circuit board to form a thermal insulation and protection mechanism, protecting the switch module from external deformation and inner damage by the high temperature during welding.Type: ApplicationFiled: December 27, 2024Publication date: July 17, 2025Inventors: CHIH YUAN WU, WEN BING HSU
-
Patent number: 12362317Abstract: A die dipping structure includes a plate including a first recessed portion having a first depth and filled with a first flux material. The plate further includes a second recessed portion, isolated from the first recessed portion, with a second depth and filled with a second flux material. The second depth is different from the first depth. The die dipping structure further includes a motor configured to move the plate so as to simultaneously dip a first die and a second die into the flux of the first recessed portion and the flux of the second recessed portion, respectively.Type: GrantFiled: February 22, 2022Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Chun Peng, Chih-Yuan Chiu, Min-Yu Wu, Yi-Kai Tu, Cheng-Lung Wu
-
Patent number: 12356658Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures formed in an array disposed over the gate electrode; and a second protection structure comprising a ring shape from a top-view perspective, and disposed over the gate dielectric layer and at a same level as the plurality of first protection structures from a cross-sectional view.Type: GrantFiled: May 21, 2024Date of Patent: July 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Huan Chen, Chien-Chih Chou, Szu-Hsien Liu, Kong-Beng Thei, Huan-Chih Yuan, Jhu-Min Song
-
Publication number: 20250216340Abstract: A method and device of inspecting a surface of an interconnect structure are provided. The interconnect structure includes a first metal layer, second metal layer, and dielectric layer enclosing the second metal layer. The first metal layer and dielectric layer are disposed above the second metal layer. At least one portion of the first metal layer is exposed from the surface of the interconnect structure. The method includes: illuminating a surface of an interconnect structure by an incident light having a first polarization state; receiving light signals reflected from the interconnect structure and having a second polarization state different from the first polarization state; and determining a planar pattern of the first metal layer by differentiating between at least one light signal reflected from the first metal layer and at least one light signal reflected from the second metal layer according to intensity differences between the light signals.Type: ApplicationFiled: March 14, 2024Publication date: July 3, 2025Inventors: CHIN-YU LIU, CHIH-YUAN LIN, HUNG-CHUN LO, CHAO-YU HUANG, CHUN-PIN HSU, CHENG-TAO TSAI
-
Publication number: 20250216343Abstract: A method and device of inspecting a surface of an interconnect structure are provided. The interconnect structure includes a metal layer and a dielectric layer having fluorescence characteristics. The method includes: generating an excitation light beam from an excitation light source; adjusting the excitation light beam to cause the excitation light beam to form an elongated light spot having a long axis and a short axis on a surface of the interconnect structure, and cause the excitation light beams for forming the elongated light spot to be incident on the surface of the interconnect structure along a direction perpendicular to the long axis of the elongated light spot; receiving a plurality of fluorescent signals generated from the dielectric layer upon excitation thereof by the elongated light spot; and determining a portion of a planar pattern of the metal layer according to the fluorescence signals.Type: ApplicationFiled: March 18, 2024Publication date: July 3, 2025Inventors: CHIH-YUAN LIN, YU-WEI LIU, FENG-JUI SHIH, HSIN-YI YEH, HUNG-CHUN LO, CHAO-YU HUANG, CHUN-PIN HSU, CHENG-TAO TSAI
-
Publication number: 20250218706Abstract: A switch structure electrically linked with a light source includes a main body, a push button assembly, and at least one contact block. The main body includes a base and an internal switch assembly. The base is provided with a plurality of power terminals for connecting to an external power source and the internal switch assembly is serially connected to between the power terminals and a light source. The contact block includes a plurality of control terminals for connecting to external devices to be controlled; and the push button assembly can drive the internal switch assembly and the contact block, so that the control terminals of the contact block are electrically connected to each other and the light source is synchronously controlled by the internal switch assembly to electrically connect to the external power source and emit light, which can indicate an operational state of the switch structure.Type: ApplicationFiled: November 12, 2024Publication date: July 3, 2025Inventors: CHIH-YUAN WU, WEN BING HSU
-
Publication number: 20250217570Abstract: A method comprising receiving, at a computing system, a request for design rules of an integrated circuit technology node; and providing, by the computing system, a plurality of design rule entries for display in a tabular format by an interface, the plurality of design rule entries selected based on the request, a design rule entry of the plurality of design rule entries corresponding to a design rule of the plurality of design rules, the design rule entry comprising a first cell designated for a label of the design rule, a second cell designated for a description of the design rule, and a third cell designated for a numerical dimension for the design rule.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Chih-Yuan Yang, Yuejun Fu, Matthew K. Gumbel, Cher-Yin Khor, Ashish V. Sangwai
-
Patent number: 12349454Abstract: Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.Type: GrantFiled: February 17, 2022Date of Patent: July 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chang Jong, Yi-Huan Chen, Chien-Chih Chou, Tsung-Chieh Tsai, Szu-Hsien Liu, Huan-Chih Yuan, Jhu-Min Song
-
Publication number: 20250210919Abstract: A power protection component is used for being assembled on a host. The power protection component includes a protective housing and an iron core. The protective housing is fixed on the outside of the host. The protective housing comprises an accommodating chamber, a first opening and a second opening. The accommodating chamber is located within the protective housing, and the first opening and the second opening are respectively formed on different sides of the protective housing. The iron core is fixed within the accommodating chamber, and the iron core comprises a perforating hole. After the power cord passes through the second opening and the perforating hole, the power cord is plugged into the plug-in position and forms an inductor with the iron core. The inductor can be used to suppress electromagnetic interference.Type: ApplicationFiled: December 3, 2024Publication date: June 26, 2025Inventors: Chih-Yuan CHANG, Chong-Lin LIU, Wen-Chih CHEN
-
Patent number: 12340158Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.Type: GrantFiled: January 4, 2024Date of Patent: June 24, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
-
Patent number: 12341057Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.Type: GrantFiled: July 20, 2022Date of Patent: June 24, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Wen Wu, Chih-Yuan Ting, Jyu-Horng Shieh
-
Patent number: 12333260Abstract: A method, computer system, and a computer program product for task assistance is provided. The present invention may include acquiring a request expression input by a user. The present invention may include identifying a request intent associated with a task based on the request expression. The present invention may include determining a response script corresponding to the request intent. The present invention may include executing the response script to complete the task and presenting the process of running the task in a user-interface (UI).Type: GrantFiled: February 21, 2023Date of Patent: June 17, 2025Assignee: International Business Machines CorporationInventors: Jin Shi, Chih-Yuan Lin, Shu-Chih Chen, Chao Yuan Huang, Pei-Yi Lin
-
Publication number: 20250189795Abstract: A mixed reality display device includes a waveguide element, an image light source, a first diffractive optical element lens array and a second diffractive optical element lens array. The image light source is located in the waveguide element. The first diffractive optical element lens array is located on a first side of the waveguide element facing a human eye, the first diffractive optical element lens array includes a plurality of diffractive optical element lenses, and any of the diffractive optical element lenses is configured to converge a light. The second diffractive optical element lens array is located on a second side of the waveguide element opposite to the first side, the second diffractive optical element lens array includes a plurality of diffractive optical element lenses, and any of the diffractive optical element lenses is configured to diverge or converge a light.Type: ApplicationFiled: May 17, 2024Publication date: June 12, 2025Inventors: Yeh-Wei YU, Ching-Cherng SUN, Chih-Yuan CHENG, Chih-Hung CHEN, Tsung-Hsun YANG, Shiuan-Huei LIN, Cheng-Chuan LIU
-
Patent number: 12327973Abstract: A conductive component structure of rail-type terminal device includes a conductive component disposed in an insulation case body. The conductive component has a first section and a second section connected with the base section. The first section and the second section are respectively formed with a bow portion, a first portion and a second portion. A load arm and an elastic unit assembled with the load arm are disposed on the first section and/or the second section. The elastic unit includes a first elastic section and a second elastic section. The load arm passes through the first elastic section and at least a part of the second elastic section. When the load arm is displaced or moved, the first elastic section and the second elastic section respectively provide tension (or pushback force) and pulling force effect so as to improve the shortcoming of the conventional terminal device.Type: GrantFiled: November 9, 2022Date of Patent: June 10, 2025Assignees: Switchlab Inc., Switchlab (Shanghai) Co., Ltd., Gaocheng Electronics Co., Ltd.Inventors: Chih-Yuan Wu, Ming-Shan Tai
-
Publication number: 20250180361Abstract: A visual vehicle-positioning fusion system and a method thereof is provided. In the method, an image point cloud map stored in a storage device is converted into a longitude and latitude database corresponding to the image point cloud map. Longitude and latitude measurement coordinates received by a positioning device are used as first location information. The longitude and latitude database is compared with the longitude and latitude measurement coordinates to generate the initial location of a vehicle. Feature matching is performed on the initial location and the image point cloud map to generate second location information of the vehicle on the image point cloud map. The first location information or the second location information is selected as a final positioning output information and outputted based on a positioning fusion rule.Type: ApplicationFiled: December 4, 2023Publication date: June 5, 2025Applicant: Automotive Research & Testing CenterInventors: Chih-Yuan HSU, Nong-Hong LIN, Ting-Fu JHU, You-Sian LIN, Shih-Hsuan LIN
-
Patent number: 12323753Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate and having acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The diaphragm includes a ventilation hole, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a protrusion extending into the air gap.Type: GrantFiled: September 19, 2022Date of Patent: June 3, 2025Assignee: FORTEMEDIA, INC.Inventors: Chih-Yuan Chen, Feng-Chia Hsu, Chun-Kai Mao, Jien-Ming Chen, Wen-Shan Lin, Nai-Hao Kuo
-
Patent number: 12317751Abstract: An integrated circuit includes a metallization pattern having first and second conductive features, an etch stop layer over the metallization pattern, a memory device, a bottom electrode via, a third conductive feature, and a dielectric feature. The etch stop layer has first and second portions over the first and second conductive features, respectively. The bottom electrode via is in the first portion of the etch stop layer and electrically connecting the memory device over the first portion of the etch stop layer to the first conductive feature. The third conductive feature is in the second portion of the etch stop layer and electrically connected to the second conductive feature. The dielectric feature is between the first and second portions of the etch stop layer and in contact with sidewalls of the first and second portions of the etch stop layer.Type: GrantFiled: July 28, 2023Date of Patent: May 27, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh, Hui-Hsien Wei
-
Patent number: D1074601Type: GrantFiled: December 14, 2022Date of Patent: May 13, 2025Assignees: Switchlab Inc., Switchlab (Shanghai) Co., Ltd., Gaocheng Electronics Co., Ltd.Inventors: Chih-Yuan Wu, Chih Kun Hsiao