Abstract: A method for detecting a seam in a film is provided. The following process is performed on a film in a first wafer: (a) a scan is performed to obtain a gray level image; (b) a region positioning process is performed on the gray level image to define target regions and a seam region located in each target region; (c) a gray level value of each pixel in each seam region is obtained, and the number of pixels whose gray level values are lower than a gray level threshold value in each seam region is calculated; (d) a pixel quantity threshold value is generated according to the number in each seam region. Then, the process (a) to (c) is performed on a film in a second wafer, and a seam region having the number exceeding the pixel quantity threshold value is determined to be a defect region.

Abstract: A semiconductor structure includes: a plurality of calibration reference features disposed on a substrate and spaced apart from each other in a first direction; and a plurality of columns of first active features and a plurality of columns of second active features respectively disposed on opposite sides of the calibration reference features, wherein each of the columns of first active features is spaced apart from each other in a second direction, each of the columns of second active features is spaced apart from each other in the second direction, and the calibration reference features, the first active features, and the second active features are disposed on the same layer and are a portion of the substrate.

Abstract: A semiconductor structure includes: a plurality of calibration reference features disposed on a substrate and spaced apart from each other in a first direction; and a plurality of columns of first active features and a plurality of columns of second active features respectively disposed on opposite sides of the calibration reference features, wherein each of the columns of first active features is spaced apart from each other in a second direction, each of the columns of second active features is spaced apart from each other in the second direction, and the calibration reference features, the first active features, and the second active features are disposed on the same layer and are a portion of the substrate.

Abstract: A recognition method for photolithography process and a semiconductor device are provided. The recognition method includes forming a mask layer on a semiconductor substrate, and then patterning the mask layer to form multiple dense line patterns in a cell region and multiple dummy dense line patterns in an interface region between the cell region and a peripheral region. At least one connection portion is provided between a first and a third dummy dense line patterns, and a second dummy dense line pattern is discontinuous at and separated from the at least one connection portion. A photoresist layer covering the peripheral region is formed on the semiconductor substrate, and whether a landing position of the photoresist layer is correct is determined according to a distance from an edge of the photoresist layer to a closest dummy dense line pattern and a width of the at least one connection portion.

Abstract: A recognition method for photolithography process and a semiconductor device are provided. The recognition method includes forming a mask layer on a semiconductor substrate, and then patterning the mask layer to form multiple dense line patterns in a cell region and multiple dummy dense line patterns in an interface region between the cell region and a peripheral region. At least one connection portion is provided between a first and a third dummy dense line patterns, and a second dummy dense line pattern is discontinuous at and separated from the at least one connection portion. A photoresist layer covering the peripheral region is formed on the semiconductor substrate, and whether a landing position of the photoresist layer is correct is determined according to a distance from an edge of the photoresist layer to a closest dummy dense line pattern and a width of the at least one connection portion.

Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.

Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.