Patents by Inventor Chih-yu Lee
Chih-yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12183712Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).Type: GrantFiled: December 27, 2022Date of Patent: December 31, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Che-Ting Liu, Jheng-Yu Hong, Yu-Ting Lu, Po-Chun Lee, Chih-Hsiang Hsu
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Patent number: 12174449Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a first movable portion, a fixed portion, a first driving assembly, and a plurality of second guiding members. The first movable portion is configured to connect an optical member. The optical member is used for adjusting a direction of a light from an incident direction to an outgoing direction. The first movable portion can move relative to the fixed portion. The first driving assembly is configured to drive the first movable portion to move relative to the fixed portion. The second guiding members include a first ball, a second ball, and a third ball. The first ball, the second ball, and the third ball are disposed in a plane that is perpendicular to the incident direction.Type: GrantFiled: January 20, 2023Date of Patent: December 24, 2024Assignee: TDK TAIWAN CORP.Inventors: Chih-Wei Weng, Chao-Chang Hu, Yueh-Lin Lee, Chen-Hsien Fan, Chien-Yu Kao, Chia-Ching Hsu, Sung-Mao Tsai, Sin-Jhong Song
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Patent number: 12170402Abstract: An electronic device includes a decoupling member, a first radiator, a second radiator, a first feed unit, a second feed unit, and a rear cover. A gap is formed between the first radiator and the second radiator, the decoupling member is indirectly coupled to the first radiator and the second radiator, and the decoupling member is disposed on a surface of the rear cover. The decoupling member does not overlap a first projection, and the first projection is a projection of the first radiator in a first direction. The decoupling member does not overlap a second projection, and the second projection is a projection of the second radiator in the first direction. The first direction is a direction perpendicular to a plane on which the rear cover is located.Type: GrantFiled: March 19, 2021Date of Patent: December 17, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Chih Yu Tsai, Chien-Ming Lee, Hanyang Wang, Dong Yu
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Publication number: 20240413223Abstract: A method for manufacturing a semiconductor structure includes: forming a channel portion on a fin portion; forming two source/drain portions on the fin portion and at two opposite sides of the channel portion, in which each of the two source/drain portions includes a first semiconductor material that is doped with dopant impurities; and forming two bottom portions each of which is disposed between the fin portion and a corresponding one of the two source/drain portions, in which each of the two bottom portions includes a second semiconductor material that is different from the first semiconductor material and that is capable of trapping the dopant impurities when the dopant impurities in the first semiconductor material diffuse toward the fin portion.Type: ApplicationFiled: June 8, 2023Publication date: December 12, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-En TSAI, Chih-Yu MA, Cheng-Han LEE, Shih-Chieh CHANG, Sheng-Syun WONG
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Publication number: 20240413221Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.Type: ApplicationFiled: July 11, 2024Publication date: December 12, 2024Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen
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Publication number: 20240408237Abstract: The present invention is related to a method and pharmaceutical composition for treating a cartilage damage in a subject (including a human or an animal), particularly osteoarthritis (OA), using extracellular vesicles (EVs) with SOX9 gene, called as “EV-SOX9”. The EV-SOX9 is obtained by encapsulating the SOX9 mRNA or the mRNA of its upstream and downstream gene in EVs, naïve EVs with high expression level of SOX9 mRNA or its upstream and downstream gene from different cell sources, or MSC-derived EV-SOX9, which is obtained by transferring the SOX9 gene or its upstream and downstream gene into a multipotent cell and collecting EVs.Type: ApplicationFiled: June 7, 2024Publication date: December 12, 2024Applicants: FAR EASTERN MEMORIAL HOSPITAL, NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Hsiu-Jung LIAO, Chih-Hung Chang, Chi-Ying Huang, Ly James Lee, Tai-Shan Cheng, Sin-Yu Chen
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Publication number: 20240404857Abstract: Base plates of a substrate retainer transportation mechanism are provided with damping members to assist elastic members in damping and limiting movement of the substrate retainer transportation mechanism when the substrate transportation mechanism is subjected to unwanted external forces, e.g., seismic forces. By damping and limiting movement of the substrate retainer transportation mechanism, undesirable damage to substrates contained in a substrate retainer being carried by the substrate retainer transport mechanism can be minimized.Type: ApplicationFiled: January 12, 2024Publication date: December 5, 2024Inventors: Chen-Hao LIAO, Pei-Yu LEE, Chih-Tsung LEE, Cheng-Lung WU, Jiun-Rong PAI
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Patent number: 12159787Abstract: In a pattern formation method, a photoresist layer is formed over a substrate by combining a first precursor and a second precursor in a vapor state to form a photoresist material. The first precursor is an organometallic having a formula MaRbXc, where M is one or more selected from the group consisting of Sn, Bi, Sb, In, and Te, R is an alkyl group that is substituted by different EDG and/or EWG, X is a halide or sulfonate group, and 1?a?2, b?1, c?1, and b+c?4. The second precursor is water, an amine, a borane, and/or a phosphine. The photoresist material is deposited over the substrate, and selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: GrantFiled: May 10, 2021Date of Patent: December 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Cheng Liu, Ming-Hui Weng, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
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Patent number: 12153346Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes a chemical formula of MaXbLc, where M is a metal, X is a multidentate aromatic ligand that includes a pyrrole-like nitrogen and a pyridine-like nitrogen, L is an extreme ultraviolet (EUV) cleavable ligand, a is between 1 and 2, b is equal to or greater than 1, and c is equal to or greater than 1.Type: GrantFiled: February 17, 2021Date of Patent: November 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
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Publication number: 20240385514Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hui WENG, Chen-Yu LIU, Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
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Publication number: 20240385523Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.Type: ApplicationFiled: July 31, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Ming-Hui WENG, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
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Publication number: 20240387173Abstract: In a pattern formation method, a photoresist layer is formed over a substrate by combining a first precursor and a second precursor in a vapor state to form a photoresist material. The first precursor is an organometallic having a formula MaRbXc, where M is one or more selected from the group consisting of Sn, Bi, Sb, In, and Te, R is an alkyl group that is substituted by different EDG and/or EWG, X is a halide or sulfonate group, and 1?a?2, b?1, c?1, and b+c?4. The second precursor is water, an amine, a borane, and/or a phosphine. The photoresist material is deposited over the substrate, and selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Cheng LIU, Ming-Hui WENG, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
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Publication number: 20240387380Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Wen-Chun Wang, Tzy-Kuang Lee, Chih-Hsien Lin, Ching-Hung Kao, Yen-Yu Chen
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Publication number: 20240385516Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes an aromatic di-dentate ligand, a transition metal coordinated to the aromatic di-dentate ligand, and an extreme ultraviolet (EUV) cleavable ligand coordinated to the transition metal. The aromatic di-dentate ligand includes a plurality of pyrazine molecules.Type: ApplicationFiled: June 28, 2024Publication date: November 21, 2024Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
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Publication number: 20240379827Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
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Publication number: 20240377732Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes a chemical formula of MaXbLc, where M is a metal, X is a multidentate aromatic ligand that includes a pyrrole-like nitrogen and a pyridine-like nitrogen, L is an extreme ultraviolet (EUV) cleavable ligand, a is between 1 and 2, b is equal to or greater than 1, and c is equal to or greater than 1.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
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Patent number: 12135501Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: GrantFiled: August 3, 2023Date of Patent: November 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Hui Weng, Chen-Yu Liu, Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
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Publication number: 20240355740Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.Type: ApplicationFiled: June 30, 2023Publication date: October 24, 2024Inventors: Feng-Yu Chang, Sheng-Hsuan Lin, Shu-Lan Chang, Kai-Yi Chu, Meng-Hsien Lin, Pei-Hsuan Lee, Pei Shan Chang, Chih-Chien Chi, Chun-I Tsai, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai, Syun-Ming Jang, Wei-Jen Lo
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Publication number: 20240355623Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: ApplicationFiled: July 2, 2024Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chen KUO, Chih-Cheng LIU, Ming-Hui WENG, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
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Patent number: 12113071Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.Type: GrantFiled: July 21, 2022Date of Patent: October 8, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Eugene I-Chun Chen, Kuan-Liang Liu, Szu-Yu Wang, Chia-Shiung Tsai, Ru-Liang Lee, Chih-Ping Chao, Alexander Kalnitsky