Abstract: An apparatus includes a laminate, the laminate including a dielectric layer having a first surface and a second surface opposed to the first surface, and a conductive layer forming a circuit element overlying the first surface of the dielectric layer. The apparatus further includes a magnetic layer over the conductive layer. A first edge surface of the magnetic layer is coplanar with a first edge surface of the laminate, and a second edge surface of the magnetic layer is coplanar with a second edge surface of the laminate.

Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate and a metallization structure over the substrate. The metallization structure includes a MIM structure, a first contact and a second contact. The MIM structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, and a top electrode layer on the ferroelectric layer. The ferroelectric layer is substantially made of lead zirconate titanate (PZT), BaTiO3 (BTO), or barium strontium titanate (BST), and a thickness of the ferroelectric layer is greater than a thickness of the dielectric layer.

Abstract: The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion, and the total volume of the first portion is greater than a total volume of the third portion.

Abstract: A color display apparatus includes a driving substrate, a color filter, a display layer and an adhesive. The color filter is faced to the driving substrate. The color filter includes a substrate and a filter layer, and the filter layer is disposed on the substrate and faced to the driving substrate. The display layer is disposed between the driving substrate and the color filter, and an orthographic projection of the display layer projecting on the filter layer is surrounded by a periphery boundary of the filter layer. An interval is existed between the orthographic projection of the display layer projecting on the filter layer and the periphery boundary of the filter layer. Besides, the adhesive is disposed between the display layer and the color filter, and a periphery boundary of the display layer and the periphery boundary of the filter layer are surrounded by the adhesive.

Abstract: A color display apparatus includes a driving substrate, a color filter and a display layer. The driving substrate has a display region and a non-display region, and at least a first alignment mark is disposed on the non-display region. The color filter is opposite to the driving substrate. The color filter includes a substrate and a filter layer disposed on the substrate. The substrate has a first region corresponding to the display region and a second region corresponding to the non-display region. The filter layer includes color filter patterns located on the first region and at least a second alignment mark located on the second region and corresponding to the first alignment mark. The display layer is disposed between the driving substrate and the color filter. Alignment precision between the driving substrate and the color filter of the color display apparatus is improved. Besides, a color filter is also provided.

Abstract: A color display apparatus includes a driving substrate, a color filter, a display layer and an adhesive. The color filter is faced to the driving substrate. The color filter includes a substrate and a filter layer, and the filter layer is disposed on the substrate and faced to the driving substrate. The display layer is disposed between the driving substrate and the color filter, and an orthographic projection of the display layer projecting on the filter layer is surrounded by a periphery boundary of the filter layer. An interval is existed between the orthographic projection of the display layer projecting on the filter layer and the periphery boundary of the filter layer. Besides, the adhesive is disposed between the display layer and the color filter, and a periphery boundary of the display layer and the periphery boundary of the filter layer are surrounded by the adhesive.

Abstract: A color display apparatus includes a driving substrate, a color filter and a display layer. The driving substrate has a display region and a non-display region, and at least a first alignment mark is disposed on the non-display region. The color filter is opposite to the driving substrate. The color filter includes a substrate and a filter layer disposed on the substrate. The substrate has a first region corresponding to the display region and a second region corresponding to the non-display region. The filter layer includes color filter patterns located on the first region and at least a second alignment mark located on the second region and corresponding to the first alignment mark. The display layer is disposed between the driving substrate and the color filter. Alignment precision between the driving substrate and the color filter of the color display apparatus is improved. Besides, a color filter is also provided.

Abstract: An electric paper display apparatus includes a substrate, a display layer and a protective layer. The display layer is disposed on the substrate. The protective layer is disposed on the display layer. The protective layer includes a bottom surface facing to the display layer and a plurality of color filter patterns disposed on the bottom surface. It does not need to dispose a color filter substrate on the protective layer of the electric paper display apparatus, so a cost and a thickness of the electric paper display apparatus can be reduced.

Abstract: A pixel structure including an active device, a first pixel electrode, a second pixel electrode, a coupling line, a common electrode, and a liquid crystal layer is provided. The first pixel electrode and the second pixel electrode have a plurality of sets of stripped electrode patterns extending along different directions, respectively, and the first pixel electrode is electrically insulated from the second pixel electrode. The coupling line is disposed under the first and the second pixel electrode and electrically insulated from the second pixel electrode. The first pixel electrode is electrically connected to the active device through the coupling line. The common electrode is disposed over the first and the second pixel electrode. The liquid crystal layer is disposed between the common electrode and the first and second pixel electrodes. Moreover, the liquid crystal layer has two polymer layers and a liquid crystal molecule layer disposed between the polymer layers.

Abstract: An active device array substrate is provided. The active device array substrate includes a plurality of pixel units. Each of the pixel units includes a first active device, a first scan line, a second active device, a second scan line, a data line, a common line, and a pixel electrode. The first scan line is electrically connected to a first gate of the first active device. The second scan line is electrically connected to a second gate of the second active device. The data line is electrically connected to a first source of the first active device. The common line is electrically connected to a second source of the second active device. The pixel electrode is electrically connected to a first drain of the first active device and a second drain of the second active device.

Abstract: An active device array substrate is provided. The active device array substrate includes a plurality of pixel units. Each of the pixel units includes a first active device, a first scan line, a second active device, a second scan line, a data line, a common line, and a pixel electrode. The first scan line is electrically connected to a first gate of the first active device. The second scan line is electrically connected to a second gate of the second active device. The data line is electrically connected to a first source of the first active device. The common line is electrically connected to a second source of the second active device. The pixel electrode is electrically connected to a first drain of the first active device and a second drain of the second active device.

Abstract: A pixel structure including an active device, a first pixel electrode, a second pixel electrode, a coupling line, a common electrode, and a liquid crystal layer is provided. The first pixel electrode and the second pixel electrode have a plurality of sets of stripped electrode patterns extending along different directions, respectively, and the first pixel electrode is electrically insulated from the second pixel electrode. The coupling line is disposed under the first and the second pixel electrode and electrically insulated from the second pixel electrode. The first pixel electrode is electrically connected to the active device through the coupling line. The common electrode is disposed over the first and the second pixel electrode. The liquid crystal layer is disposed between the common electrode and the first and second pixel electrodes. Moreover, the liquid crystal layer has two polymer layers and a liquid crystal molecule layer disposed between the polymer layers.

Abstract: A pixel structure including an active device, a first pixel electrode, a second pixel electrode, a coupling line, a common electrode, and a liquid crystal layer is provided. The first pixel electrode and the second pixel electrode have a plurality of sets of stripped electrode patterns extending along different directions, respectively, and the first pixel electrode is electrically insulated from the second pixel electrode. The coupling line is disposed under the first and the second pixel electrode and electrically insulated from the second pixel electrode. The first pixel electrode is electrically connected to the active device through the coupling line. The common electrode is disposed over the first and the second pixel electrode. The liquid crystal layer is disposed between the common electrode and the first and second pixel electrodes. Moreover, the liquid crystal layer has two polymer layers and a liquid crystal molecule layer disposed between the polymer layers.

Abstract: A pixel structure including an active device, a first pixel electrode, a second pixel electrode, a coupling line, a common electrode, and a liquid crystal layer is provided. The first pixel electrode and the second pixel electrode have a plurality of sets of stripped electrode patterns extending along different directions, respectively, and the first pixel electrode is electrically insulated from the second pixel electrode. The coupling line is disposed under the first and the second pixel electrode and electrically insulated from the second pixel electrode. The first pixel electrode is electrically connected to the active device through the coupling line. The common electrode is disposed over the first and the second pixel electrode. The liquid crystal layer is disposed between the common electrode and the first and second pixel electrodes. Moreover, the liquid crystal layer has two polymer layers and a liquid crystal molecule layer disposed between the polymer layers.

Abstract: A liquid crystal display panel including a first conductive substrate, a second conductive substrate and a liquid crystal layer is provided. The first conductive substrate includes a base, a first protrusion, a second protrusion and a photo-spacer. The first protrusion and the second protrusion disposed above the base are symmetric with respect to a central line. The second protrusion is a mirror reflection structure of the first protrusion with respect to the central line. The photo-spacer substantially disposed on the central line and positioned above the base is positioned between the first protrusion and the second protrusion. The second conductive substrate is parallel to the first conductive substrate. The liquid crystal layer is disposed between the first conductive substrate and the second conductive substrate.

Abstract: A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.