Patents by Inventor Chih-Yu Tsai

Chih-Yu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972537
    Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: April 30, 2024
    Assignee: YU JUNG CHANG TECHNOLOGY CO., LTD.
    Inventors: Chih-Chuan Chen, Wei-Hsiang Tsai, Chin-Yu Chen, Ching-Cherng Sun, Jann-Long Chern, Yu-Kai Lin
  • Patent number: 11939664
    Abstract: A semiconductor process system includes a process chamber. The process chamber includes a wafer support configured to support a wafer. The system includes a bell jar configured to be positioned over the wafer during a semiconductor process. The interior surface of the bell jar is coated with a rough coating. The rough coating can include zirconium.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Chun Hsieh, Tsung-Yu Tsai, Hsing-Yuan Huang, Chih-Chang Wu, Szu-Hua Wu, Chin-Szu Lee
  • Publication number: 20240096756
    Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240069299
    Abstract: An optical element driving mechanism includes a movable assembly, a fixed assembly, and a driving assembly. The movable assembly is configured to be connected to an optical element. The movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly in a range of motion. The optical element driving mechanism further includes a positioning assembly configured to position the movable assembly at a predetermined position relative to the fixed assembly when the driving assembly is not operating.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Inventors: Chao-Chang HU, Kuen-Wang TSAI, Liang-Ting HO, Chao-Hsi WANG, Chih-Wei WENG, He-Ling CHANG, Che-Wei CHANG, Sheng-Zong CHEN, Ko-Lun CHAO, Min-Hsiu TSAI, Shu-Shan CHEN, Jungsuck RYOO, Mao-Kuo HSU, Guan-Yu SU
  • Patent number: 11916128
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11916282
    Abstract: An antenna apparatus includes a feeding antenna inside an electronic device and one or more antenna elements, such as a floating metal antenna, disposed on a rear cover of the electronic device. The floating metal antenna and a feeding antenna inside the electronic device may form a coupling antenna structure. The feeding antenna may be an antenna fastened on an antenna support (which may be referred to as a support antenna). The feeding antenna may alternatively be a slot antenna formed by slitting on a metal middle frame of the electronic device. The antenna apparatus may be implemented in limited design space, thereby effectively saving antenna design space inside the electronic device. The antenna apparatus may generate excitation of a plurality of resonance modes, so that antenna bandwidth and radiation characteristics can be improved.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: February 27, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Pengfei Wu, Chien-Ming Lee, Dong Yu, Chih Yu Tsai, Chih-Hua Chang, Arun Sowpati
  • Patent number: 11699550
    Abstract: An inductor structure includes a first curve metal component, a second curve metal component, a connection component, and a capacitor. The first and the second curve metal components are disposed on a layer. The layer is located at a first plane, the first and the second curve metal components are located at a second plane. The connection component is coupled to the first curve metal component and the second curve metal component. A first terminal of the connection component is coupled to a first terminal of the first curve metal component. A second terminal of the connection component is coupled to a first terminal of the second curve metal component. A first terminal of the capacitor is coupled to a second terminal of the first curve metal component. A second terminal of the capacitor is coupled to a second terminal of the second curve metal component.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: July 11, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Chih-Yu Tsai, Kai-Yi Huang
  • Publication number: 20230141980
    Abstract: An embodiment of this application provides an electronic device, including a decoupling member, a first radiator, a second radiator, a first feed unit, a second feed unit, and a rear cover. A gap is formed between the first radiator and the second radiator, the decoupling member is indirectly coupled to the first radiator and the second radiator, and the decoupling member is disposed on a surface of the rear cover. The decoupling member does not overlap a first projection, and the first projection is a projection of the first radiator on the rear cover in a first direction. The decoupling member does not overlap a second projection, and the second projection is a projection of the second radiator on the rear cover in the first direction. The first direction is a direction perpendicular to a plane on which the rear cover is located.
    Type: Application
    Filed: March 19, 2021
    Publication date: May 11, 2023
    Inventors: Chih Yu Tsai, Chien-Ming Lee, Hanyang Wang, Dong Yu
  • Patent number: 11616012
    Abstract: A patterned shielding structure is disposed between an inductor structure and a substrate. The patterned shielding structure includes a shielding layer and a first stacked structure. The shielding layer extends along a plane. The first stacked structure is stacked, along a first direction, on the shielding layer. The first direction is perpendicular to the plane. The first stacked structure has a crossed shape and is configured to enhance a shielding effect.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 28, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Kuan-Yu Shih, Chih-Yu Tsai, Ka-Un Chan
  • Publication number: 20210376452
    Abstract: An antenna apparatus includes a feeding antenna inside an electronic device and one or more antenna elements, such as a floating metal antenna, disposed on a rear cover of the electronic device. The floating metal antenna and a feeding antenna inside the electronic device may form a coupling antenna structure. The feeding antenna may be an antenna fastened on an antenna support (which may be referred to as a support antenna). The feeding antenna may alternatively be a slot antenna formed by slitting on a metal middle frame of the electronic device. The antenna apparatus may be implemented in limited design space, thereby effectively saving antenna design space inside the electronic device. The antenna apparatus may generate excitation of a plurality of resonance modes, so that antenna bandwidth and radiation characteristics can be improved.
    Type: Application
    Filed: November 5, 2019
    Publication date: December 2, 2021
    Inventors: Pengfei WU, Chien-Ming LEE, Dong YU, Chih Yu TSAI, Chih-Hua CHANG, Arun SOWPATI
  • Publication number: 20210090988
    Abstract: A patterned shielding structure is disposed between an inductor structure and a substrate. The patterned shielding structure includes a shielding layer and a first stacked structure. The shielding layer extends along a plane. The first stacked structure is stacked, along a first direction, on the shielding layer. The first direction is perpendicular to the plane. The first stacked structure has a crossed shape and is configured to enhance a shielding effect.
    Type: Application
    Filed: March 26, 2020
    Publication date: March 25, 2021
    Inventors: Hsiao-Tsung YEN, Kuan-Yu SHIH, Chih-Yu TSAI, Ka-Un CHAN
  • Publication number: 20210050147
    Abstract: An inductor structure includes a first curve metal component, a second curve metal component, a connection component, and a capacitor. The first and the second curve metal components are disposed on a layer. The layer is located at a first plane, the first and the second curve metal components are located at a second plane. The connection component is coupled to the first curve metal component and the second curve metal component. A first terminal of the connection component is coupled to a first terminal of the first curve metal component. A second terminal of the connection component is coupled to a first terminal of the second curve metal component. A first terminal of the capacitor is coupled to a second terminal of the first curve metal component. A second terminal of the capacitor is coupled to a second terminal of the second curve metal component.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Inventors: Hsiao-Tsung YEN, Chih-Yu TSAI, Kai-Yi HUANG
  • Patent number: 10867746
    Abstract: An inductor structure includes a first curve metal component, a second curve metal component, and a connection component. The first curve metal component is disposed on a layer. The layer is located at a first plane, the first curve metal component is located at a second plane, and the first plane is perpendicular to the second plane. The second curve metal component is disposed on the layer. The second curve metal component is located at the second plane. The connection component is coupled to the first curve metal component and the second curve metal component.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 15, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Chih-Yu Tsai, Kai-Yi Huang
  • Patent number: 10367266
    Abstract: A multi-antenna communication device is provided, including a grounding conductor plane separating a first side space and a second side space and having a first edge. A four-antenna array including first, second, third and fourth antennas is located at the first edge, and has an overall maximum array length extending along the first edge. The first and second antennas are located in the first side space, and the third and fourth antennas are located in the second side space. Each of the first to fourth antennas includes a feeding conductor line, a grounding conductor line, and a radiating conductor portion electrically connected to a signal source through the feeding conductor line and electrically connected to the first edge through the grounding conductor line, thereby forming a loop path and generating at least one resonant mode. The radiating conductor portion has a corresponding projection line segment at the first edge.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: July 30, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Kin-Lu Wong, Jun-Yu Lu, De-Ming Chian, Wei-Yu Li, Chih-Yu Tsai
  • Patent number: 10263336
    Abstract: A multi-band multi-antenna array includes a ground conductor plane and a dual antenna array. The ground conductor plane includes a first edge and separates a first side space and a second side space. The dual antenna array has a maximum array length extending along the first edge and includes a first antenna and a second antenna. The first antenna includes a first resonant loop and a first radiating conductor line exciting the first antenna generating a first resonant mode and a second resonant mode, respectively, wherein frequencies of the first resonant mode are lower than frequencies of the second resonant mode. The second antenna includes a second resonant loop and a second radiating conductor line exciting the first antenna generating a third resonant mode and a fourth resonant mode, respectively, wherein frequencies of the third resonant mode are lower than frequencies of the fourth resonant mode.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 16, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Kin-Lu Wong, Wei-Yu Li, Chih-Yu Tsai
  • Patent number: 10074587
    Abstract: The present invention discloses a bonding-wire-type heat sink structure for semiconductor devices. An embodiment of the said bonding-wire-type heat sink structure comprises: a semiconductor substrate; a heat source formed on or included in the semiconductor substrate, said heat source including at least one hot spot; at least one heat conduction layer; at least one heat conductor connecting the at least one hot spot with the at least one heat conduction layer; at least one heat dissipation component in an electrically floating state; and at least one bonding wire connecting the at least one heat conduction layer with the at least one heat dissipation component, so as to transmit the heat of the heat source to the heat dissipation component.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: September 11, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Chih-Yu Tsai, Cheng-Wei Luo
  • Publication number: 20180183132
    Abstract: A multi-antenna communication device is provided, including a grounding conductor plane separating a first side space and a second side space and having a first edge. A four-antenna array including first, second, third and fourth antennas is located at the first edge, and has an overall maximum array length extending along the first edge. The first and second antennas are located in the first side space, and the third and fourth antennas are located in the second side space. Each of the first to fourth antennas includes a feeding conductor line, a grounding conductor line, and a radiating conductor portion electrically connected to a signal source through the feeding conductor line and electrically connected to the first edge through the grounding conductor line, thereby forming a loop path and generating at least one resonant mode. The radiating conductor portion has a corresponding projection line segment at the first edge.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Inventors: Kin-Lu Wong, Jun-Yu Lu, De-Ming Chian, Wei-Yu Li, Chih-Yu Tsai
  • Publication number: 20170271234
    Abstract: The present invention discloses a bonding-wire-type heat sink structure for semiconductor devices. An embodiment of the said bonding-wire-type heat sink structure comprises: a semiconductor substrate; a heat source formed on or included in the semiconductor substrate, said heat source including at least one hot spot; at least one heat conduction layer; at least one heat conductor connecting the at least one hot spot with the at least one heat conduction layer; at least one heat dissipation component in an electrically floating state; and at least one bonding wire connecting the at least one heat conduction layer with the at least one heat dissipation component, so as to transmit the heat of the heat source to the heat dissipation component.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 21, 2017
    Inventors: HSIAO-TSUNG YEN, CHIH-YU TSAI, CHENG-WEI LUO
  • Patent number: 9729121
    Abstract: The present invention discloses an LC tank capable of reducing electromagnetic radiation by itself and the manufacturing method of the same. An embodiment of said LC tank comprises: a first tank area whose boundary is defined by a first part of an inductance; a second tank area whose boundary is defined by a second part of the inductance in which the second part includes a gap; a cross-interconnection structure operable to electrically connect the first and second parts of the inductance and distinguish the first tank area from the second tank area; and at least one capacitance formed inside at least one of the first and second tank areas, wherein the area ratio of the first tank area to the second tank area is between 20% and 80%.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: August 8, 2017
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Yu Tsai, Kai-Yi Huang, Hsiao-Tsung Yen