Patents by Inventor Chih Yuan Chien
Chih Yuan Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240089607Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.Type: ApplicationFiled: May 29, 2023Publication date: March 14, 2024Applicant: HTC CorporationInventors: Chao Shuan Huang, Sheng-Long Wu, Yu-Jui Hsu, Shih-Yao Tsai, Tun-Hao Chao, Sen-Lin Chung, Chih Pin Chung, Chih-Yuan Chien, Shih Hong Sun
-
Publication number: 20240071413Abstract: The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Western Digital Technologies, Inc.Inventors: Ming MAO, Yung-Hung WANG, Chih-Ching HU, Chen-Jung CHIEN, Carlos CORONA, Hongping YUAN, Ming JIANG, Goncalo Marcos BAIÃO DE ALBUQUERQUE
-
Publication number: 20220223567Abstract: A semiconductor package includes a first semiconductor die, an adhesive layer, a second semiconductor die, a plurality of conductive pillars and an encapsulant. The adhesive layer is adhered to the first semiconductor die. The second semiconductor die is stacked over the first semiconductor die. The conductive pillars surround the first semiconductor die.Type: ApplicationFiled: March 31, 2022Publication date: July 14, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Fu Kao, Chih-Yuan Chien, Li-Hui Cheng, Szu-Wei Lu
-
Patent number: 11296051Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor packages includes a first semiconductor die, an adhesive layer, a second semiconductor die and an underfill. The first semiconductor die includes a first surface, and the first surface includes a central region and a peripheral region surrounding the central region. The adhesive layer is adhered to the peripheral region and exposes the central region. The second semiconductor die is stacked over the first surface of the first semiconductor die. The underfill is disposed between the first semiconductor die and the second semiconductor die.Type: GrantFiled: August 22, 2019Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Fu Kao, Chih-Yuan Chien, Li-Hui Cheng, Szu-Wei Lu
-
Publication number: 20210057384Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor packages includes a first semiconductor die, an adhesive layer, a second semiconductor die and an underfill. The first semiconductor die includes a first surface, and the first surface includes a central region and a peripheral region surrounding the central region. The adhesive layer is adhered to the peripheral region and exposes the central region. The second semiconductor die is stacked over the first surface of the first semiconductor die. The underfill is disposed between the first semiconductor die and the second semiconductor die.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Fu Kao, Chih-Yuan Chien, Li-Hui Cheng, Szu-Wei Lu
-
Patent number: 10867849Abstract: A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.Type: GrantFiled: December 16, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Hui Cheng, Chin-Fu Kao, Chih-Yuan Chien, Szu-Wei Lu
-
Patent number: 10867955Abstract: A package structure includes a substrate, a die, an adhesive layer, a dam structure, and an encapsulant. The die is disposed on the substrate. The adhesive layer is disposed between the substrate and the die. The adhesive layer has a curved surface. The dam structure is disposed on the substrate and surrounded by the adhesive layer. The encapsulant encapsulates the die.Type: GrantFiled: January 21, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Hui Cheng, Chin-Fu Kao, Chih-Yuan Chien, Szu-Wei Lu
-
Publication number: 20200144110Abstract: A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.Type: ApplicationFiled: December 16, 2019Publication date: May 7, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hui Cheng, Chin-Fu Kao, Chih-Yuan Chien, Szu-Wei Lu
-
Publication number: 20200105705Abstract: A package structure includes a substrate, a die, an adhesive layer, a dam structure, and an encapsulant. The die is disposed on the substrate. The adhesive layer is disposed between the substrate and the die. The adhesive layer has a curved surface. The dam structure is disposed on the substrate and surrounded by the adhesive layer. The encapsulant encapsulates the die.Type: ApplicationFiled: January 21, 2019Publication date: April 2, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hui Cheng, Chin-Fu Kao, Chih-Yuan Chien, Szu-Wei Lu
-
Publication number: 20200006133Abstract: A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.Type: ApplicationFiled: August 15, 2018Publication date: January 2, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hui Cheng, Chin-Fu Kao, Chih-Yuan Chien, Szu-Wei Lu
-
Patent number: 10510591Abstract: A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.Type: GrantFiled: August 15, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hui Cheng, Chin-Fu Kao, Chih-Yuan Chien, Szu-Wei Lu
-
Patent number: 10165613Abstract: A control method, suitable for an electronic device, includes following operations. A first connection is established based on a classic Bluetooth protocol or a Bluetooth Low Energy protocol from the electronic device to a first target device. A Bluetooth identifier of the first target device acquired in the first connection is recorded. The Bluetooth identifier of the first target device is shared. The Bluetooth identifier is utilized to establish a second connection based on the classic Bluetooth protocol or the Bluetooth Low Energy protocol to the first target device. The first connection and the second connection are established based on different protocols.Type: GrantFiled: March 30, 2017Date of Patent: December 25, 2018Assignee: HTC CorporationInventors: Lo-Chien Lee, Chih-Yuan Chien, Kai-Hsiu Chen, Wen-Yuan Chen
-
Publication number: 20180103499Abstract: A control method, suitable for an electronic device, includes following operations. A first connection is established based on a classic Bluetooth protocol or a Bluetooth Low Energy protocol from the electronic device to a first target device. A Bluetooth identifier of the first target device acquired in the first connection is recorded. The Bluetooth identifier of the first target device is shared. The Bluetooth identifier is utilized to establish a second connection based on the classic Bluetooth protocol or the Bluetooth Low Energy protocol to the first target device. The first connection and the second connection are established based on different protocols.Type: ApplicationFiled: March 30, 2017Publication date: April 12, 2018Inventors: Lo-Chien LEE, Chih-Yuan CHIEN, Kai-Hsiu CHEN, Wen-Yuan CHEN
-
Patent number: 8952534Abstract: A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least another portion of the pad region. The bump structure is electrically connected to the pad region via the opening. The bump structure includes a copper layer and a SnAg layer overlying the copper layer. The SnAg layer has a melting temperature higher than the eutectic temperature of Sn and Ag.Type: GrantFiled: November 19, 2013Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jen Lai, Chih-Kang Han, Chien-Pin Chan, Chih-Yuan Chien, Huai-Tei Yang
-
Patent number: 8896591Abstract: A pixel circuit includes a first sub-pixel and a second sub-pixel. The first sub-pixel is coupled to a scan line and a data line, so as to determine whether to be enabled according to a first scan signal transmitted on the scan line, and whether to be driven according to a data signal transmitted on the data line. The second sub-pixel is coupled to the scan line, so as to determine whether to be enabled according to the first scan signal. The data signal is in a first state when the first scan signal is in a pre-charged period. The data signal is in a second state during a time interval after the pre-charged period is over and before the first scan signal enters a turn-on period. Voltage polarities of the first state and the second state are opposite. The pixel design can improve color shift and frame flicker.Type: GrantFiled: May 5, 2014Date of Patent: November 25, 2014Assignee: Au Optronics CorporationInventors: Chih-Yuan Chien, Chien-Hua Chen, Chen-Kuo Yang, Hsueh-Ying Huang
-
Publication number: 20140240309Abstract: A pixel circuit includes a first sub-pixel and a second sub-pixel. The first sub-pixel is coupled to a scan line and a data line, so as to determine whether to be enabled according to a first scan signal transmitted on the scan line, and whether to be driven according to a data signal transmitted on the data line. The second sub-pixel is coupled to the scan line, so as to determine whether to be enabled according to the first scan signal. The data signal is in a first state when the first scan signal is in a pre-charged period. The data signal is in a second state during a time interval after the pre-charged period is over and before the first scan signal enters a turn-on period. Voltage polarities of the first state and the second state are opposite. The pixel design can improve color shift and frame flicker.Type: ApplicationFiled: May 5, 2014Publication date: August 28, 2014Applicant: Au Optronics CorporationInventors: Chih-Yuan Chien, Chien-Hua Chen, Chen-Kuo Yang, Hsueh-Ying Huang
-
Patent number: 8766970Abstract: A pixel circuit includes a first sub-pixel and a second sub-pixel. The first sub-pixel is coupled to a scan line and a data line, so as to determine whether to be enabled according to a first scan signal transmitted on the scan line, and whether to be driven according to a data signal transmitted on the data line. The second sub-pixel is coupled to the scan line, so as to determine whether to be enabled according to the first scan signal. The data signal is in a first state when the first scan signal is in a pre-charged period. The data signal is in a second state during a time interval after the pre-charged period is over and before the first scan signal enters a turn-on period. Voltage polarities of the first state and the second state are opposite. The pixel design can improve color shift and frame flicker.Type: GrantFiled: October 24, 2008Date of Patent: July 1, 2014Assignee: Au Optronics CorporationInventors: Chih-Yuan Chien, Chien-Hua Chen, Chen-Kuo Yang, Hsueh-Ying Huang
-
Publication number: 20140070409Abstract: A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least another portion of the pad region. The bump structure is electrically connected to the pad region via the opening. The bump structure includes a copper layer and a SnAg layer overlying the copper layer. The SnAg layer has a melting temperature higher than the eutectic temperature of Sn and Ag.Type: ApplicationFiled: November 19, 2013Publication date: March 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Jen LAI, Chih-Kang HAN, Chien-Pin CHAN, Chih-Yuan CHIEN, Huai-Tei YANG
-
Patent number: 8610270Abstract: A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.Type: GrantFiled: February 9, 2010Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jen Lai, Chih-Kang Han, Chien-Pin Chan, Chih-Yuan Chien, Huai-Tei Yang
-
Patent number: 8373811Abstract: A liquid crystal display (LCD) device essentially includes a plurality of data lines, a plurality of gate lines and a plurality of pixel units. Each pixel unit includes a first liquid-crystal capacitor, a second liquid-crystal capacitor, a first switch and a second switch. The first liquid-crystal capacitor of a pixel unit is charged via the first switch of the same pixel unit. The second liquid-crystal capacitor of a pixel unit is charged via the second switch of the same pixel unit and the first switch of a different pixel unit. The sub-pixel voltages corresponding to the first and second liquid-crystal capacitors of the same pixel unit have the same polarity. Furthermore, disclosed is a liquid-crystal display driving method for writing two data signals having same polarity respectively into the first and second liquid-crystal capacitors of a pixel unit via the same date line during two intervals partly overlapped.Type: GrantFiled: June 26, 2008Date of Patent: February 12, 2013Assignee: AU Optronics Corp.Inventors: Chih-Yuan Chien, Pei-Yi Chen