Patents by Inventor Chih-Yuan CHIU

Chih-Yuan CHIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006690
    Abstract: A bonded assembly may be formed by performing a chip plasma clean process on a semiconductor chip; generating at least one chip infrared image of a cleaned side of the semiconductor chip; measuring an average emissivity of at least one metallic region in the at least one chip infrared image; performing a subsequent processing step selected from a bonding step and an alternative processing step based on the measured average emissivity. The bonding step is performed if the measured average emissivity is less than a predetermined emissivity threshold value. The alternative processing step is performed if the measured average emissivity is greater than the predetermined emissivity threshold value. The alternative processing step may be selected from an additional clean step and an additional inspection step.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Inventors: Amram Eitan, Jen-Hao Liu, Chih-Yuan Chiu, Hui-Ting Lin, Chi-Chun Peng
  • Publication number: 20240404988
    Abstract: A bonded assembly may be formed by providing at least a first packaging substrate in a low-oxygen ambient; providing at least a first semiconductor package in the low-oxygen ambient; performing a first plasma package-treatment process on the first semiconductor package in the low-oxygen ambient by directing at least one first plasma jet to first solder material portions bonded to the first semiconductor package; and bringing the first solder material portions onto, or in proximity to, first substrate-side bonding structures located on the first packaging substrate while the at least one first plasma jet is directed to the first solder material portions. The first substrate-side bonding structures are treated with the first plasma jet. The first semiconductor package is bonded to the first packaging substrate while, or after, the first substrate-side bonding structures are treated with the first plasma jet.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Hui-Min Huang, Kai Jun Zhan, Ming-Da Cheng, Chih-Yuan Chiu, Amram Eitan
  • Publication number: 20240404989
    Abstract: A bonded assembly may be formed by providing a wafer comprising at least a first packaging substrate and a second packaging substrate in a low-oxygen ambient; performing a first plasma package-treatment process on the first semiconductor package in the low-oxygen ambient while performing a first substrate-treatment process on the first packaging substrate in a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa; and performing a second plasma package-treatment process on the second semiconductor package while performing a second substrate-treatment process on the second packaging substrate and while bonding the first semiconductor package to the first packaging substrate.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Hui-Min Huang, Kai Jun Zhan, Chih-Yuan Chiu, Ming-Da Cheng, Amram Eitan
  • Publication number: 20240404839
    Abstract: A bonded assembly may be formed by: providing a substrate and a semiconductor chip in a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa; disposing the semiconductor chip on the substrate; performing a plasma treatment process on a copper-containing surface of a chip bonding pad on the semiconductor chip in the low-oxygen ambient by directing a plasma jet to the chip bonding pad; and attaching a bonding wire to the semiconductor chip and to the substrate such that a first end of the bonding wire is attached to the copper-containing surface and a second end of the bonding wire is attached to a substrate bonding pad on the substrate.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Hui-Min Huang, Chang-Jung Hsueh, Chih-Yuan Chiu, Jen-Hao Liu, Ming-Da Cheng, Amram Eitan
  • Publication number: 20240297143
    Abstract: A bonding tool and a bonding method are provided. The method includes attaching a semiconductor die to a bonding tool having a first surface, wherein the bonding tool comprises a bending member movably arranged in a trench of the bonding tool, and the bending member protrudes from the first surface and bends the semiconductor die; moving the semiconductor die toward a semiconductor wafer to cause a retraction of the bending member and a partial bonding at a portion of the semiconductor die and the semiconductor wafer; and causing a full bonding between the semiconductor die and the semiconductor wafer subsequent to the partial bonding.
    Type: Application
    Filed: May 3, 2024
    Publication date: September 5, 2024
    Inventors: CHIH-YUAN CHIU, SHIH-YEN CHEN, CHI-CHUN PENG, HONG-KUN CHEN, HUI-TING LIN
  • Publication number: 20240194633
    Abstract: A die bonding tool includes a bond head that secures a semiconductor die against a planar surface of the bond head, an actuator system that moves the bond head and the semiconductor die towards a surface of a target substrate, and at least one contact sensor configured to detect an initial contact between a first region of the semiconductor die and the surface of the target substrate, where in response to detecting the initial contact between the semiconductor die and the target substrate, the actuator tilts the planar surface of the bond head and the semiconductor die to bring a second region of the semiconductor die into contact with the surface of the target substrate and thereby provide improved contact between the semiconductor die and the target substrate and more effective bonding including instances where the planar surface of the bond head and the target substrate surface are not parallel.
    Type: Application
    Filed: March 23, 2023
    Publication date: June 13, 2024
    Inventors: Amram Eitan, Hui-Ting Lin, Chien-Hung Chen, Chih-Yuan Chiu, Kai Jun Zhan
  • Patent number: 12009337
    Abstract: A bonding tool and a bonding method are provided. The method includes attaching a semiconductor die to a bonding tool having a first surface, wherein the bonding tool comprises a bending member movably arranged in a trench of the bonding tool, and the bending member protrudes from the first surface and bends the semiconductor die; moving the semiconductor die toward a semiconductor wafer to cause a retraction of the bending member and a partial bonding at a portion of the semiconductor die and the semiconductor wafer; and causing a full bonding between the semiconductor die and the semiconductor wafer subsequent to the partial bonding.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yuan Chiu, Shih-Yen Chen, Chi-Chun Peng, Hong-Kun Chen, Hui-Ting Lin
  • Publication number: 20230032570
    Abstract: A bonding tool and a bonding method are provided. The method includes attaching a semiconductor die to a bonding tool having a first surface, wherein the bonding tool comprises a bending member movably arranged in a trench of the bonding tool, and the bending member protrudes from the first surface and bends the semiconductor die; moving the semiconductor die toward a semiconductor wafer to cause a retraction of the bending member and a partial bonding at a portion of the semiconductor die and the semiconductor wafer; and causing a full bonding between the semiconductor die and the semiconductor wafer subsequent to the partial bonding.
    Type: Application
    Filed: February 15, 2022
    Publication date: February 2, 2023
    Inventors: CHIH-YUAN CHIU, SHIH-YEN CHEN, CHI-CHUN PENG, HONG-KUN CHEN, HUI-TING LIN
  • Publication number: 20230023353
    Abstract: A die dipping structure includes a plate including a first recessed portion having a first depth and filled with a first flux material. The plate further includes a second recessed portion, isolated from the first recessed portion, with a second depth and filled with a second flux material. The second depth is different from the first depth. The die dipping structure further includes a motor configured to move the plate so as to simultaneously dip a first die and a second die into the flux of the first recessed portion and the flux of the second recessed portion, respectively.
    Type: Application
    Filed: February 22, 2022
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Chun Peng, Chih-Yuan Chiu, Min-Yu Wu, Yi-Kai Tu, Cheng-Lung Wu
  • Patent number: 10312118
    Abstract: A bonding apparatus includes a wafer stage, a first chip stage, a first chip transporting device, a second stage and a second chip transporting device. The wafer stage is used for holding a wafer. The first chip stage is used for holding at least one first chip. The first chip transporting device is used for transporting the first chip from the first chip stage onto the wafer. The second chip stage is used for holding at least one second chip. The second chip transporting device is used for transporting the second chip from the second chip stage onto the wafer.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Shan Wu, Yi-Ting Hu, Ming-Tan Lee, Yu-Lin Wang, Yuh-Sen Chang, Pin-Yi Shin, Wen-Ming Chen, Wei-Chih Chen, Chih-Yuan Chiu
  • Publication number: 20150200118
    Abstract: A bonding apparatus includes a wafer stage, a first chip stage, a first transporting device, a second stage and a second transporting device. The wafer stage is used for holding a wafer. The first chip stage is used for holding at least one first chip. The first transporting device is used for transporting the first chip from the first chip stage onto the wafer. The second chip stage is used for holding at least one second chip. The second transporting device is used for transporting the second chip from the second chip stage onto the wafer.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 16, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Shan WU, Yi-Ting HU, Ming-Tan LEE, Yu-Lin WANG, Yuh-Sen CHANG, Pin-Yi SHIN, Wen-Ming CHEN, Wei-Chih CHEN, Chih-Yuan CHIU