Patents by Inventor Chih-Yuan Hsiao

Chih-Yuan Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11762439
    Abstract: The present invention provides a method of dynamic thermal management applied to a portable device, wherein the method includes the steps of: obtaining a surface temperature of the portable device; obtaining a junction temperature of a chip of the portable device; and calculating an upper limit of the junction temperature according to the junction temperature and the surface temperature.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 19, 2023
    Assignee: MEDIATEK INC.
    Inventors: Pei-Yu Huang, Chih-Yuan Hsiao, Chiao-Pin Fan, Chi-Wen Pan, Tai-Yu Chen, Chien-Tse Fang, Jih-Ming Hsu, Yun-Ching Li
  • Patent number: 11253867
    Abstract: Dry nano-sizing equipment with fluid mobility effect dryly processes viewable fine-grained substances into a nano-sized dimension by high-pressure airflow resulted from a pressure-generating unit, as well as high-speed fluid and high mechanical momentum generated in a pressure cylinder by high-speed rotation of a booster impeller.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 22, 2022
    Inventors: Chih-Yuan Hsiao, Yu-Chih Hsiao
  • Publication number: 20210181821
    Abstract: The present invention provides a method of dynamic thermal management applied to a portable device, wherein the method includes the steps of: obtaining a surface temperature of the portable device; obtaining a junction temperature of a chip of the portable device; and calculating an upper limit of the junction temperature according to the junction temperature and the surface temperature.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 17, 2021
    Inventors: Pei-Yu Huang, Chih-Yuan Hsiao, Chiao-Pin Fan, Chi-Wen Pan, Tai-Yu Chen, Chien-Tse Fang, Jih-Ming Hsu, Yun-Ching Li
  • Publication number: 20210053070
    Abstract: Dry nano-sizing equipment with fluid mobility effect dryly processes viewable fine-grained substances into a nano-sized dimension by high-pressure airflow resulted from a pressure-generating unit, as well as high-speed fluid and high mechanical momentum generated in a pressure cylinder by high-speed rotation of a booster impeller.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 25, 2021
    Inventors: Chih-Yuan HSIAO, Yu-Chih HSIAO
  • Patent number: 10127883
    Abstract: A frame rate control method is provided. The frame rate control method includes the following step: detecting a frame rate of an image signal generated by an image processing apparatus to generate a first detection result; detecting a system load on the image processing apparatus to generate a second detection result; and determining whether to provide a frame rate limit to limit the frame rate according to at least the first detection result and the second detection result.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: November 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Wei-Ting Wang, Yingshiuan Pan, Chih-Yuan Hsiao, Chien-Ming Chiu
  • Publication number: 20180232032
    Abstract: A power management method for an electronic apparatus is provided. The electronic apparatus includes a plurality of heat sources. The power management method includes the following steps: detecting a temperature of the electronic apparatus; detecting a power of the electronic apparatus; identifying an operating scenario of the electronic apparatus; and referring to the detected temperature, the detected power and the operating scenario to determine whether to allocate a power budget between the heat sources.
    Type: Application
    Filed: February 15, 2017
    Publication date: August 16, 2018
    Inventors: Wei-Ting Wang, Yingshiuan Pan, Han-Lin Li, Chih-Yuan Hsiao, Che-Chuan Hu
  • Patent number: 9898797
    Abstract: Techniques pertaining to thermal management for smooth variation in display frame rate are described. A method may involve performing either or both of: (1) determining whether a temperature of at least one portion of an electronic apparatus exceeds a temperature threshold; and (2) determining whether a variation in a frame rate of images displayed on a display device associated with the electronic apparatus exceeds a variation threshold. The method may also involve controlling the frame rate in response to either or both of a first determination that the monitored temperature exceeds the temperature threshold and a second determination that the variation in the frame rate exceeds the variation threshold.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: February 20, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chih-Yuan Hsiao, Wei-Ting Wang, Jih-Cheng Chiu
  • Publication number: 20180026451
    Abstract: A mobile device performs thermal management during concurrent battery charging and workload execution based on a thermal headroom. The thermal headroom is an amount of power, in a form of heat, that heat dissipation hardware in the mobile device is estimated to dissipate when the mobile device operates at a target temperature. After the thermal headroom is determined, the mobile device determines a first power allocation to system loading, which is caused by one or more applications running on the mobile device. The first power allocation is subtracted from the thermal headroom to obtain a second power allocation to a charger, which charges a battery module of the mobile device while the one or more application are running. The mobile device then sets an input power limit of the charger based on the second power allocation.
    Type: Application
    Filed: March 28, 2017
    Publication date: January 25, 2018
    Inventors: Chih-Yuan Hsiao, Chien-Tse Fang, Wei-Ting Wang, Yung-Cheng Huang, Jia-You Chuang
  • Publication number: 20170116951
    Abstract: A frame rate control method is provided. The frame rate control method includes the following step: detecting a frame rate of an image signal generated by an image processing apparatus to generate a first detection result; detecting a system load on the image processing apparatus to generate a second detection result; and determining whether to provide a frame rate limit to limit the frame rate according to at least the first detection result and the second detection result.
    Type: Application
    Filed: June 14, 2016
    Publication date: April 27, 2017
    Inventors: Wei-Ting Wang, Yingshiuan Pan, Chih-Yuan Hsiao, Chien-Ming Chiu
  • Publication number: 20160328821
    Abstract: Techniques pertaining to thermal management for smooth variation in display frame rate are described. A method may involve performing either or both of: (1) determining whether a temperature of at least one portion of an electronic apparatus exceeds a temperature threshold; and (2) determining whether a variation in a frame rate of images displayed on a display device associated with the electronic apparatus exceeds a variation threshold. The method may also involve controlling the frame rate in response to either or both of a first determination that the monitored temperature exceeds the temperature threshold and a second determination that the variation in the frame rate exceeds the variation threshold.
    Type: Application
    Filed: July 19, 2016
    Publication date: November 10, 2016
    Inventors: Chih-Yuan Hsiao, Wei-Ting Wang, Jih-Cheng Chiu
  • Patent number: 9105505
    Abstract: A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: August 11, 2015
    Assignee: INOTERA MEMORIES, INC.
    Inventors: Chien-Chi Lee, Chia-Ming Yang, Wei-Ping Lee, Hsin-Huei Chen, Chih-Yuan Hsiao, Ping Kao, Kai-Lun Chiang, Chao-Sung Lai, Jer-Chyi Wang
  • Publication number: 20140312401
    Abstract: A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.
    Type: Application
    Filed: September 12, 2013
    Publication date: October 23, 2014
    Applicant: INOTERA MEMORIES, INC.
    Inventors: Chien-Chi Lee, Chia-Ming Yang, Wei-Ping Lee, Hsin-Huei Chen, Chih-Yuan Hsiao, Ping Kao, Kai-Lun Chiang, Chao-Sung Lai, Jer-Chyi Wang
  • Patent number: 7845057
    Abstract: A crank puller includes a nut portion having a front end for screwing into a threaded hole on a crank, and an internally threaded bore; a bolt portion screwed through the threaded bore and having a front conical-bottomed hole; a head portion fitted in the conical-bottomed hole and having a front end with an annular groove for receiving an elastic element therein; and a cap portion assembled around the front end of the head portion for pressing against a crank axle, and being replaceable corresponding to a diametrical size of the crank axle.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: December 7, 2010
    Assignee: Lifu Bicycle Co., Ltd.
    Inventor: Chih Yuan Hsiao
  • Patent number: 7211483
    Abstract: A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: May 1, 2007
    Assignee: Nanya Technology Corporation
    Inventors: Yi-Nan Chen, Hui-Min Mao, Chih-Yuan Hsiao, Ming-Cheng Chang
  • Patent number: 7009236
    Abstract: A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: March 7, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Yi-Nan Chen, Hui-Min Mao, Chih-Yuan Hsiao, Ming-Cheng Chang
  • Patent number: 6987053
    Abstract: A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: January 17, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Wen-Bin Wu, Chih-Yuan Hsiao, Hui-Min Mao
  • Publication number: 20050167719
    Abstract: A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.
    Type: Application
    Filed: February 28, 2005
    Publication date: August 4, 2005
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Nan Chen, Hui-Min Mao, Chih-Yuan Hsiao, Ming-Cheng Chang
  • Publication number: 20050168740
    Abstract: A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.
    Type: Application
    Filed: March 25, 2005
    Publication date: August 4, 2005
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Wen-Bin Wu, Chih-Yuan Hsiao, Hui-Min Mao
  • Patent number: 6872629
    Abstract: A method of forming a memory cell with a single sided buried strap. A collar oxide layer is formed on the sidewall of a trench. A conductive layer fills the trench. The conductive layer and the collar oxide layer are partially removed to form an opening having first and second sidewalls. The remaining collar oxide layer is lower than the remaining conductive layer. An angle implantation with F ions is performed on the first sidewall. A thermal oxidation process is performed to form a first oxide layer on the first sidewall and a second oxide layer on the second sidewall. The first oxide layer is thicker than the second oxide layer. The second oxide layer is removed to expose the second sidewall. A buried strap is formed at the bottom of the opening, insulated from the first sidewall by the first oxide layer.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: March 29, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Chih-Yuan Hsiao, Yi-Nan Chen
  • Publication number: 20050048654
    Abstract: A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.
    Type: Application
    Filed: March 3, 2004
    Publication date: March 3, 2005
    Inventors: Wen-Bin Wu, Chih-Yuan Hsiao, Hui-Min Mao