Patents by Inventor Chih-Yuan Hsu

Chih-Yuan Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240203109
    Abstract: A computer vision vehicle locating fusion method includes: receiving an instant driving image from a camera, extracting multiple image features from the instant driving image and the multiple image features being extracted with the pre-stored feature sets in the storage device to fuse an inertial measurement parameter and the pre-stored satellite locating coordinate corresponding to one of the pre-stored feature sets that best matches the instant driving image to generate a first candidate coordinate; using the one satellite measurement coordinate received from a satellite locating device as a second candidate coordinate; calculating a first difference between the first candidate coordinate and an estimated reference coordinate, and calculating a second difference between the second candidate coordinate and the estimated reference coordinate; and determining and outputting the first candidate coordinate or the second candidate coordinate that has the smaller difference with the estimated reference coordinate.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Applicant: AUTOMOTIVE RESEARCH & TESTING CENTER
    Inventors: Chih-Yuan HSU, Te-Hsiang WANG, You-Sian LIN
  • Publication number: 20240170381
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan CAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
  • Patent number: 11991840
    Abstract: This disclosure is directed to an electronic device having a casing, a circular frame, and a display. A panel is arranged on one side of the casing, a circular opening is defined on the panel, and a first fixing structure is arranged on an inner edge of the circular opening. The circular frame is rotatably arranged in the circular opening to close the circular opening, a second fixing structure is arranged on an outer edge of the circular frame, and the second fixing structure is limited by the first fixing structure. The display is embedded in the circular frame and exposed on the panel, so that the display is rotatable according to various placing positions of the casing.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: May 21, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chia-Yuan Lin, Chih-Yuan Hsu, Chung-Chieh Cheng
  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Publication number: 20240153943
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 9, 2024
    Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
  • Publication number: 20240153790
    Abstract: Processing chambers including at least one gas reservoir connected to and in fluid communication with the lid through a fast-switching valve and a gas reservoir line are described. Processing methods, for example, etching methods, using the processing chambers are also described.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 9, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Borui Xia, Chih-Hsun Hsu, Xiaoxiong Yuan, Le Zhang, David T. Or, Jiang Lu
  • Patent number: 11943584
    Abstract: A micro-electro-mechanical system (MEMS) microphone is provided. The MEMS microphone includes a substrate, a diaphragm, a backplate and a first protrusion. The substrate has an opening portion. The diaphragm is disposed on one side of the substrate and extends across the opening portion of the substrate. The backplate includes a plurality of acoustic holes. The backplate is disposed on one side of the diaphragm. An air gap is formed between the backplate and the diaphragm. The first protrusion extends from the backplate towards the air gap.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: March 26, 2024
    Assignee: FORTEMEDIA, INC.
    Inventors: Chih-Yuan Chen, Jien-Ming Chen, Feng-Chia Hsu, Wen-Shan Lin, Nai-Hao Kuo
  • Publication number: 20240087961
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Ju CHOU, Chih-Chung Chang, Jun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Kao, Chen-Hsuan Liao
  • Publication number: 20240089607
    Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.
    Type: Application
    Filed: May 29, 2023
    Publication date: March 14, 2024
    Applicant: HTC Corporation
    Inventors: Chao Shuan Huang, Sheng-Long Wu, Yu-Jui Hsu, Shih-Yao Tsai, Tun-Hao Chao, Sen-Lin Chung, Chih Pin Chung, Chih-Yuan Chien, Shih Hong Sun
  • Publication number: 20240086612
    Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
  • Patent number: 11929314
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 11923250
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Patent number: 11916060
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
  • Patent number: 11792358
    Abstract: A video transmitting circuit and a signal delay compensation method thereof are provided. The video transmitting circuit transmits a specific signal through a first transmission path and a second transmission path to a video receiver during a calibration mode. In the calibration mode, a return detection circuit of the video transmitting circuit detects whether or not a first return signal transmitted through the first transmission path and a second return signal transmitted through the second transmission path have been received by the video transmitting circuit. The video transmitting circuit sets delay circuits serially connected in the first or second transmission path according to a detection result of the return detection circuit, such that the first return signal transmitted through the first transmission path and the second return signal transmitted through the second transmission path can synchronously arrive at the video receiver.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: October 17, 2023
    Assignee: ALI CORPORATION
    Inventors: Fong-Shen Wong, Jian-Shiang Fang, Chih-Yuan Hsu
  • Patent number: 11762409
    Abstract: The disclosure provides a voltage regulator with a soft-start effect. The voltage regulator includes an amplifier, a first voltage setting circuit, a voltage selector and a power transistor. The amplifier has two input terminals to receive respectively a reference voltage and a feedback voltage. The amplifier has a current source to provide a current to an output terminal. In a voltage bypass mode, the first voltage setting circuit increases a driving voltage on the output terminal according to the current based on a selection voltage. In the voltage bypass mode, the voltage selector sequentially reduces the selection voltage respectively in multiple time intervals in a startup time interval. The power transistor receives the driving voltage, and generates an output voltage according to the driving voltage based on an operating power supply.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: September 19, 2023
    Assignee: ALi Corporation
    Inventors: Chih-Yuan Hsu, Andrew Yang Lee
  • Patent number: 11747844
    Abstract: A voltage regulator including an amplifier, a start signal generator and a power transistor is provided. The amplifier has a first positive input terminal, a second positive input terminal, and a negative input terminal to receive a start signal, a reference voltage and a feedback voltage respectively. An output terminal of the amplifier generates a driving voltage. The start signal generator is coupled to the first positive input terminal of the amplifier and generates the start signal, which is incremental, during a startup time interval in a voltage bypass mode. The power transistor generates an output voltage according to the driving voltage based on an operating power. In the voltage bypass mode, the reference voltage is equal to the operating power. A soft-start effect can be effectively achieved by the voltage regulator in the voltage bypass mode.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: September 5, 2023
    Assignee: ALi Corporation
    Inventors: Chih-Yuan Hsu, Chien-Yuan Lu
  • Publication number: 20230268186
    Abstract: A method of producing an epitaxial semiconductor wafer includes measuring one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus. The method also includes polishing a semiconductor wafer using a polishing assembly and measuring the polished semiconductor wafer to determine a surface profile of the polished wafer. The method further includes generating a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus. The method also includes determining a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjusting, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 24, 2023
    Inventors: Chih-Yuan Hsu, Chun-Chin TU, Yau-Ching Yang, Shih-Chiang Chen
  • Patent number: 11703899
    Abstract: A voltage regulator, including an amplifier, a voltage setting circuit and a power transistor, is provided. The amplifier includes a first current source and a second current source. The amplifier has two input terminals to respectively receive a reference voltage and a feedback voltage. The first current source is coupled between the operating power source and an output terminal of the amplifier, and provides a first current to the output terminal. The second current source is coupled between the output terminal and a reference ground terminal, and draws a second current from the output terminal. The voltage setting circuit is coupled to the output terminal, and increases a driving voltage on the output terminal according to the first current in a voltage bypass mode. The power transistor receives the driving voltage and generates an output voltage according to the driving voltage based on the operating power source.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: July 18, 2023
    Assignee: ALi Corporation
    Inventors: Chih-Yuan Hsu, Andrew Yang Lee
  • Publication number: 20230201994
    Abstract: A polishing head assembly for polishing of semiconductor wafers includes a polishing head and a cap. The polishing head has a recess along a bottom portion. The recess has a recessed surface. The cap is positioned within the recess. The cap includes an annular wall secured to the polishing head and a floor joined to the annular wall at a joint. The floor extends across the annular wall, and the floor has an upper surface and a lower surface. The upper surface is spaced from the recessed surface to form a chamber therebetween. A deformation resistance of a portion of the floor proximate the joint is weakened to allow the portion of the floor proximate the joint to deflect relative to the polishing head by a change of pressure in the chamber.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 29, 2023
    Inventors: Chih Yuan Hsu, Jen Chieh Lin, Chieh Hu, Wei Chang Huang, Yau-Ching Yang
  • Publication number: 20230058284
    Abstract: This disclosure is directed to an electronic device having a casing, a circular frame, and a display. A panel is arranged on one side of the casing, a circular opening is defined on the panel, and a first fixing structure is arranged on an inner edge of the circular opening. The circular frame is rotatably arranged in the circular opening to close the circular opening, a second fixing structure is arranged on an outer edge of the circular frame, and the second fixing structure is limited by the first fixing structure. The display is embedded in the circular frame and exposed on the panel, so that the display is rotatable according to various placing positions of the casing.
    Type: Application
    Filed: January 3, 2022
    Publication date: February 23, 2023
    Inventors: Chia-Yuan LIN, Chih-Yuan HSU, Chung-Chieh CHENG