Abstract: Processing chambers including at least one gas reservoir connected to and in fluid communication with the lid through a fast-switching valve and a gas reservoir line are described. Processing methods, for example, etching methods, using the processing chambers are also described.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: A micro-electro-mechanical system (MEMS) microphone is provided. The MEMS microphone includes a substrate, a diaphragm, a backplate and a first protrusion. The substrate has an opening portion. The diaphragm is disposed on one side of the substrate and extends across the opening portion of the substrate. The backplate includes a plurality of acoustic holes. The backplate is disposed on one side of the diaphragm. An air gap is formed between the backplate and the diaphragm. The first protrusion extends from the backplate towards the air gap.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.

Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: A video transmitting circuit and a signal delay compensation method thereof are provided. The video transmitting circuit transmits a specific signal through a first transmission path and a second transmission path to a video receiver during a calibration mode. In the calibration mode, a return detection circuit of the video transmitting circuit detects whether or not a first return signal transmitted through the first transmission path and a second return signal transmitted through the second transmission path have been received by the video transmitting circuit. The video transmitting circuit sets delay circuits serially connected in the first or second transmission path according to a detection result of the return detection circuit, such that the first return signal transmitted through the first transmission path and the second return signal transmitted through the second transmission path can synchronously arrive at the video receiver.

Abstract: The disclosure provides a voltage regulator with a soft-start effect. The voltage regulator includes an amplifier, a first voltage setting circuit, a voltage selector and a power transistor. The amplifier has two input terminals to receive respectively a reference voltage and a feedback voltage. The amplifier has a current source to provide a current to an output terminal. In a voltage bypass mode, the first voltage setting circuit increases a driving voltage on the output terminal according to the current based on a selection voltage. In the voltage bypass mode, the voltage selector sequentially reduces the selection voltage respectively in multiple time intervals in a startup time interval. The power transistor receives the driving voltage, and generates an output voltage according to the driving voltage based on an operating power supply.

Abstract: A voltage regulator including an amplifier, a start signal generator and a power transistor is provided. The amplifier has a first positive input terminal, a second positive input terminal, and a negative input terminal to receive a start signal, a reference voltage and a feedback voltage respectively. An output terminal of the amplifier generates a driving voltage. The start signal generator is coupled to the first positive input terminal of the amplifier and generates the start signal, which is incremental, during a startup time interval in a voltage bypass mode. The power transistor generates an output voltage according to the driving voltage based on an operating power. In the voltage bypass mode, the reference voltage is equal to the operating power. A soft-start effect can be effectively achieved by the voltage regulator in the voltage bypass mode.

Abstract: A method of producing an epitaxial semiconductor wafer includes measuring one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus. The method also includes polishing a semiconductor wafer using a polishing assembly and measuring the polished semiconductor wafer to determine a surface profile of the polished wafer. The method further includes generating a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus. The method also includes determining a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjusting, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.

Abstract: A voltage regulator, including an amplifier, a voltage setting circuit and a power transistor, is provided. The amplifier includes a first current source and a second current source. The amplifier has two input terminals to respectively receive a reference voltage and a feedback voltage. The first current source is coupled between the operating power source and an output terminal of the amplifier, and provides a first current to the output terminal. The second current source is coupled between the output terminal and a reference ground terminal, and draws a second current from the output terminal. The voltage setting circuit is coupled to the output terminal, and increases a driving voltage on the output terminal according to the first current in a voltage bypass mode. The power transistor receives the driving voltage and generates an output voltage according to the driving voltage based on the operating power source.

Abstract: A polishing head assembly for polishing of semiconductor wafers includes a polishing head and a cap. The polishing head has a recess along a bottom portion. The recess has a recessed surface. The cap is positioned within the recess. The cap includes an annular wall secured to the polishing head and a floor joined to the annular wall at a joint. The floor extends across the annular wall, and the floor has an upper surface and a lower surface. The upper surface is spaced from the recessed surface to form a chamber therebetween. A deformation resistance of a portion of the floor proximate the joint is weakened to allow the portion of the floor proximate the joint to deflect relative to the polishing head by a change of pressure in the chamber.

Abstract: This disclosure is directed to an electronic device having a casing, a circular frame, and a display. A panel is arranged on one side of the casing, a circular opening is defined on the panel, and a first fixing structure is arranged on an inner edge of the circular opening. The circular frame is rotatably arranged in the circular opening to close the circular opening, a second fixing structure is arranged on an outer edge of the circular frame, and the second fixing structure is limited by the first fixing structure. The display is embedded in the circular frame and exposed on the panel, so that the display is rotatable according to various placing positions of the casing.

Abstract: A method for manufacturing an electronic device is provided, the method includes: providing an inspection module to inspect a first area of the electronic device to obtain a first information and inspect a second area of the electronic device to obtain a second information; transmitting the first information and the second information to a processing system; comparing the first information and the second information to obtain a difference; and transmitting a correction information to a first process machine via a first interface system. When the difference is greater than or equal to -2 and less than or equal to 2, the first process machine is started to produce. An electronic device is also provided.

Abstract: A polishing head assembly for polishing of semiconductor wafers includes a polishing head and a cap. The polishing head has a top portion and a recess along a bottom portion. The recess has a recessed surface. Holes extend from the top portion through the recessed surface. The cap is positioned within the recess and the cap has an annular wall and a floor extending across the annular wall. The annular wall has apertures corresponding to the holes. The floor is spaced from the recessed surface to form a chamber therebetween. The polishing head assembly also includes a band that circumscribes a portion of the annular wall. The holes and the corresponding apertures receive fasteners to removably secure the annular wall to the recessed surface.

Abstract: A carrier positioning device includes a carrying base (100) and a carrier (200). A clamp (110) is arranged on the carrying base (100) and a protruding hook (113) protrudes from one side of a distal end (111) of the clamp (110). The carrier (200) has a pipe (210), and a joint (220) is disposed at one end of the pipe (210). The protruding hook (113) hooks one side of the joint (220) so that at least another portion of the carrier (200) is in contact with the carrying base (100). Accordingly, the carrier (200) can be quickly installed or be removed along a lateral direction.

Abstract: A method for capturing a tool path, applicable to a machine tool having a controller and furnished with a tooling, includes the steps of: obtaining a data update frequency of the controller; calculating a feed rate of the controller, determining whether or not the feed rate is obtained, going to next step if positive, and going to the previous step if negative; reading G-codes of the controller to confirm the feed rate; and, based on the confirmed feed rate, recording machine coordinates transmitted from the controller for synthesizing a tool path file. The tool path file is used for simulation and analysis of machining of the machine tool. In addition, a device for capturing the tool path is also provided.