Patents by Inventor Chih-Yuan Shih

Chih-Yuan Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563589
    Abstract: A certificate management system includes an electronic device and a server. The electronic device is configured to transmit a certificate application request. The server is configured to sign a device certificate corresponding to the electronic device through an intermediate certificate device after receiving the certificate application request, and transmit the device certificate and the Internet address of the server to the electronic device. The electronic device stores the device certificate and the Internet address of the server to complete the certificate issuance operation.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: January 24, 2023
    Assignee: MOXA INC.
    Inventors: Chi-Yuan Kao, Yu-Chen Kao, Hung-Chun Chen, Chih-Hsiung Shih
  • Patent number: 11538681
    Abstract: An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a silicon substrate and a silicon carbide layer. The silicon substrate has a first surface and a second surface opposite to each other, and the first surface is an epitaxy surface. The silicon carbide layer is located in the silicon substrate, and a distance between the silicon carbide layer and the first surface is between 100 angstroms (?) and 500 angstroms.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: December 27, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Ying-Ru Shih, Chih-Yuan Chuang, Chun-I Fan, Wen-Ching Hsu
  • Patent number: 11477038
    Abstract: A certificate transfer system includes a first certificate management host and a certificate transfer management host. The first certificate management host is configured to generate a first certificate, sign an electronic device with the first certificate, and transmit a first Internet address to the electronic device to complete a certificate-issuance operation. The certificate transfer management host is configured to store a transfer device list and a second Internet address. When the first certificate management host receives the first certificate issued by the electronic device, the first certificate management host verifies that the first certificate is correct and determines that if the first certificate matches one of the certificates in the transfer device list, the first certificate management host returns the certificate transfer management host address to the electronic device.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: October 18, 2022
    Assignee: MOXA INC.
    Inventors: Chi-Yuan Kao, Yu-Chen Kao, Hung-Chun Chen, Chih-Hsiung Shih
  • Patent number: 11476572
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: October 18, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Publication number: 20220328690
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 13, 2022
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Patent number: 11450661
    Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Hsu, Yi-Tang Lin, Clement Hsingjen Wann, Chih-Sheng Chang, Wei-Chun Tsai, Jyh-Cherng Sheu, Chi-Yuan Shih
  • Patent number: 11437325
    Abstract: An electronic package is provided and has a packaging substrate including a ground pad and a power pad. The power pad surrounds at least three directions of the ground pad so as to increase the footprint of the power pad on the packaging substrate, thereby avoiding cracking of an electronic element disposed on the packaging substrate and effectively reducing the voltage drop.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: September 6, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan Lin, Hsiu-Fang Chien, Chih-Yuan Shih, Tsung-Li Lin
  • Publication number: 20220223634
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a higher reflectivity than the first material.
    Type: Application
    Filed: January 8, 2021
    Publication date: July 14, 2022
    Inventors: Che Wei Yang, Sheng-Chan Li, Tsun-Kai Tsao, Chih-Cheng Shih, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 11374127
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Publication number: 20210358851
    Abstract: An electronic package is provided and has a packaging substrate including a ground pad and a power pad. The power pad surrounds at least three directions of the ground pad so as to increase the footprint of the power pad on the packaging substrate, thereby avoiding cracking of an electronic element disposed on the packaging substrate and effectively reducing the voltage drop.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 18, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan Lin, Hsiu-Fang Chien, Chih-Yuan Shih, Tsung-Li Lin
  • Publication number: 20200328142
    Abstract: A package stack structure and a method for fabricating the same are provided. An electronic component is disposed on the topmost one of a plurality of organic material substrates, and no chip is disposed on the remaining organic material substrates. A predefined layer number of circuit layers are disposed in the organic material substrates, and distributes the thermal stress via the organic material substrates. Therefore, the bottommost one of the organic material substrates will not be separated from a circuit board due to CTE mismatch. Also a carrier component is provided.
    Type: Application
    Filed: August 12, 2019
    Publication date: October 15, 2020
    Inventors: Don-Son Jiang, Nai-Hao Kao, Chih-Sheng Lin, Szu-Hsien Chen, Chih-Yuan Shih, Chia-Cheng Chen, Yu-Cheng Pai, Hsuan-Hao Mi
  • Publication number: 20200161756
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Patent number: 10587041
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 10, 2020
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Patent number: 10096541
    Abstract: A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: October 9, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ching-Wen Chiang, Hsin-Chih Wang, Chih-Yuan Shih, Shih-Ching Chen
  • Publication number: 20180090835
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Application
    Filed: May 16, 2017
    Publication date: March 29, 2018
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Publication number: 20170330826
    Abstract: A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.
    Type: Application
    Filed: August 1, 2017
    Publication date: November 16, 2017
    Inventors: Ching-Wen Chiang, Hsin-Chih Wang, Chih-Yuan Shih, Shih-Ching Chen
  • Patent number: 9754868
    Abstract: A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: September 5, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ching-Wen Chiang, Hsin-Chih Wang, Chih-Yuan Shih, Shih-Ching Chen
  • Publication number: 20170194238
    Abstract: A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 6, 2017
    Inventors: Ching-Wen Chiang, Hsin-Chih Wang, Chih-Yuan Shih, Shih-Ching Chen
  • Patent number: 9058971
    Abstract: An electro-optical module is provided, which includes: a substrate having a first surface with a groove and an opposite second surface; a plurality of support members disposed on the first surface of the substrate; at least an electro-optical element having opposite active and non-active surfaces and disposed in the groove of the substrate via the non-active surface thereof; an interposer disposed on the first surface of the substrate and the electro-optical element for electrically connecting the electro-optical element to the substrate, wherein the interposer has a through hole corresponding in position to the active surface of the electro-optical element; and a transparent plate disposed over the first surface of the substrate and the interposer through the support members and having a lens portion corresponding in position to the through hole of the interposer, thereby reducing signal losses, improving alignment precision, and achieving preferred thermal dissipation and EMI shielding effects.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: June 16, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Yuan Shih, Shih-Liang Peng, Jung-Pin Huang, Chin-Yu Ku, Hsien-Wen Chen
  • Publication number: 20140192832
    Abstract: An electro-optical module is provided, which includes: a substrate having a first surface with a groove and an opposite second surface; a plurality of support members disposed on the first surface of the substrate; at least an electro-optical element having opposite active and non-active surfaces and disposed in the groove of the substrate via the non-active surface thereof; an interposer disposed on the first surface of the substrate and the electro-optical element for electrically connecting the electro-optical element to the substrate, wherein the interposer has a through hole corresponding in position to the active surface of the electro-optical element; and a transparent plate disposed over the first surface of the substrate and the interposer through the support members and having a lens portion corresponding in position to the through hole of the interposer, thereby reducing signal losses, improving alignment precision, and achieving preferred thermal dissipation and EMI shielding effects.
    Type: Application
    Filed: May 30, 2013
    Publication date: July 10, 2014
    Inventors: Chih-Yuan Shih, Shih-Liang Peng, Jung-Pin Huang, Chin-Yu Ku, Hsien-Wen Chen