Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin, the gate structure comprising: a first metallic layer; a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element; and an oxide layer between the first metallic layer and the second metallic layer.

Abstract: A modular AC/DC power conversion module for power sources and loads and a method of driving the same is provided. When an AC/DC converter is electrically coupled to an external power source, a microprocessor is electrically energized by a buck auxiliary circuit, under control of the microprocessor, a DC/DC converter is activated for a certain time period, and then, the AC/DC converter is activated. Thereafter, an output voltage of the AC/DC converter is boosted, and an output voltage of the DC/DC converter is boosted accordingly. Power elements in the downstream side DC/DC converter are activated first, and then power elements in the upstream side AC/DC converter are activated, thereby an inrush current is suppressed. Once the external power source is connected, the buck auxiliary circuit will automatically reduce a voltage of the power input to activate the module. It realizes that the module will autonomously operate after being electrically energized.

Abstract: A semiconductor device and a method of manufacturing thereof are provided. The method comprises: forming a gate electrode over a substrate; forming source/drain regions beside the gate electrode; forming contact plugs on the source/drain regions; forming a dielectric layer over the contact plugs and the gate electrode; forming first openings and a second opening in the dielectric layer to expose portions of the contact plugs and a portion of the gate electrode respectively; performing a pre-clean process such as applying an ozone-containing source to the exposed portions of the contact plugs and the gate electrode; performing a surface treatment to the first and second openings to passivate sidewalls of the first and second openings; forming a conductive layer to fill the first openings and the second opening in a same deposition process by using a same metal precursor; and performing a planarization process.

Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

Abstract: The present disclosure describes a semiconductor device having a dielectric structure between a source/drain (S/D) structure and a contact structure. The semiconductor device includes a S/D structure on a substrate, a dielectric structure on a top surface of the S/D structure, and a S/D contact structure on the S/D structure and the dielectric structure. A portion of the S/D contact structure is in contact with a top surface of the dielectric structure.

Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Abstract: Gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.

Abstract: An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.

Abstract: An integrated circuit includes a nanosheet transistor having a plurality of stacked channels, a gate electrode surrounding the stacked channels, a source/drain region, and a source/drain contact. The integrated circuit includes a first dielectric layer between the gate metal and the source/drain contact, a second dielectric layer on the first dielectric layer, and a cap metal on the first gate metal and on a hybrid fin structure. The second dielectric layer is on the hybrid fin structure between the cap metal and the source/drain contact.

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

Abstract: A method for processing a curved plastic panel is to first form a hard coating layer, an optical function layer, and a printing layer on a flat plastic substrate, and then cut it into a predetermined shape, and then use a hot pressing and curving device to perform a hot pressing and curving process to the flat plastic substrate in order to make it becoming a curved plastic substrate. The hot pressing and curving device can simultaneously perform hot pressing during the heating process, and has the functions of real-time monitoring of the local temperature and the local curvature forming state, and then feedback to the local heating and curvature forming mechanism for adjustments. The monitoring of temperature and curvature can be divided into multiple stages, which can be monitored stage by stage and adjusted for heating or curvature forming to improve production yield.

Abstract: Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source/drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source/drain contacts are formed in a self-aligned manner.

Abstract: An integrated circuit includes a substrate having a semiconductor layer. The integrated circuit includes a transistor. The transistor includes stacked channels above the semiconductor layer, a first source/drain region in contact with the channels, and a second source/drain region in contact with the channels. A backside source/drain contact is positioned in the substrate directly below and electrically coupled to the first source/drain region. A frontside source/drain contact is directly above and electrically coupled to the first source/drain region. A bottom semiconductor structure is positioned below the second source/drain region and in contact with the semiconductor layer.

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.

Abstract: A package structure and a method for forming the same are provided. The package structure includes a first package structure and a second package structure. The first package structure includes a first device formed over a first substrate. The first device includes a first conductive plug connected to a through substrate via (TSV) structure formed in the first substrate. A buffer layer surrounds the first substrate. A first bonding layer is formed over the first substrate and the buffer layer. The second package structure includes a second device formed over a second substrate. A second bonding layer is formed over the second device. A hybrid bonding structure is between the first package structure and the second package structure by bonding the first bonding layer to the second bonding layer.

Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

Abstract: A light-guide sunroof assembly comprises a plastic substrate and a light source module furnished besides the plastic substrate. An outer layer of the plastic substrate is added with dye to form a colored background. A plurality of light-guide microstructures is furnished on the plastic substrate to guide the light generated by the light source module toward an inner surface of the plastic substrate. Thereby, the light generated by the light source module is guided by the plastic substrate and then ejects out of the inner surface of plastic substrate, so as to provide a light decoration or lighting effect that enriches the visual experience. Moreover, the plastic substrate is first formed into a curved plastic plate through a hot pressing process, and then a connecting structure is formed and fixed on the plastic plate by an insert-molding injection process, in order to replace the traditional car sunroof mechanism which is assembled by glass plate bonded with metal connecting parts.

Abstract: A semiconductor processing tool includes: a process chamber into which a semiconductor wafer is loaded; a support for securing the wafer loaded into the chamber tool; an inlet which introduces a first gas into the chamber for processing the wafer; and an exhaust system that exhausts gas from the chamber. The exhaust system includes: a first line coupled to the chamber to exhaust gas from the chamber; and a pump to draw gas through the first line from the chamber. The tool further includes a heating module having: a second line coupled to the first and a supply of a second gas, the second gas being flowed through the second line from the supply into the first line; and a heating element contained in the second line, the heating element heating the second gas in the second line before the second gas is flowed into the first line.