Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: A test method includes: generating an error correction code according to a base data; dividing the base data into a plurality of base data sections; generating a plurality of candidate testing data according to the base data, wherein each of the candidate testing data has a plurality of testing data sections, and each of the testing data sections corresponds to each of the base data sections; and, performing a plurality of testing schemes. Each of the testing schemes includes: generating a plurality of write-in test data according to the plurality of candidate testing data, and writing the plurality of write-in test data with the error correction code into a tested device continuously; reading a plurality of mode register values of the tested device and a plurality of readout data from the tested device; and generating a test result according to the plurality of mode register value and the readout data.