Patents by Inventor Chih-Yuan Wen

Chih-Yuan Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250014941
    Abstract: An isolation structure of a semiconductor device includes a substrate, a first isolation structure and a second isolation structure. The substrate has a first region and a second region, and there is a boundary between the first region and the second region. The first isolation structure is disposed in the first region of the substrate, and the first isolation structure includes a dielectric liner and a first insulating layer. The second isolation structure is disposed in the second region of the substrate, and the second isolation structure includes a second insulating layer. The first isolation structure and the second isolation structure are respectively located on both sides of the boundary.
    Type: Application
    Filed: July 31, 2023
    Publication date: January 9, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yuan Wen, Lung-En Kuo, Chung-Yi Chiu
  • Publication number: 20240420991
    Abstract: A semiconductor device with a deep trench isolation and a shallow trench isolation includes a substrate. The substrate is divided into a high voltage transistor region and a low voltage transistor region. A deep trench is disposed within the high voltage transistor region. The deep trench includes a first trench and a second trench. The first trench includes a first bottom. The second trench extends from the first bottom toward a bottom of the substrate. A first shallow trench and a second shallow trench are disposed within the low voltage transistor region. A length of the first shallow trench is the same as a length of the second trench. An insulating layer fills in the first trench, the second trench, the first shallow trench and the second shallow trench.
    Type: Application
    Filed: July 7, 2023
    Publication date: December 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jing-Wen Huang, Chih-Yuan Wen, Lung-En Kuo, Po-Chang Lin, Kun-Yuan Liao, Chung-Yi Chiu
  • Patent number: 11955989
    Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.
    Type: Grant
    Filed: August 21, 2022
    Date of Patent: April 9, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Yuan Wen
  • Publication number: 20240063823
    Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.
    Type: Application
    Filed: August 21, 2022
    Publication date: February 22, 2024
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Yuan Wen
  • Patent number: 11852680
    Abstract: A test method includes: generating an error correction code according to a base data; dividing the base data into a plurality of base data sections; generating a plurality of candidate testing data according to the base data, wherein each of the candidate testing data has a plurality of testing data sections, and each of the testing data sections corresponds to each of the base data sections; and, performing a plurality of testing schemes. Each of the testing schemes includes: generating a plurality of write-in test data according to the plurality of candidate testing data, and writing the plurality of write-in test data with the error correction code into a tested device continuously; reading a plurality of mode register values of the tested device and a plurality of readout data from the tested device; and generating a test result according to the plurality of mode register value and the readout data.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: December 26, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Yuan Wen