Patents by Inventor Chih-Yuan Wu

Chih-Yuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363559
    Abstract: A structure includes a first via and a first conductive line embedded in a first dielectric layer and spaced apart from each other by the first dielectric layer. A first metal pattern disposed on the first via and embedded in a second dielectric layer. A first conductive via disposed on the first conductive line and embedded in the second dielectric layer. The first metal pattern and the first conductive via are spaced apart from each other and are located on a first horizontal level, and the first metal pattern has an open ring shape. A second via disposed on the first metal pattern and embedded in a third dielectric layer. An inductor structure including the first via, the first metal pattern, and the second via.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Chang, Jiun-Yi Wu, Chien-Hsun Lee, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240363684
    Abstract: A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source/drain features on opposite sides of the dummy gate structures and over the first fin, forming second source/drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source/drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source/drain features, and forming second silicide features over the second source/drain features.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Chun-Yuan CHEN, Lo-Heng CHANG, Huan-Chieh SU, Chih-Hao WANG, Szu-Chien WU
  • Patent number: 12125848
    Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Ching Wang, Chun-Chung Su, Chung-Wei Wu, Jon-Hsu Ho, Kuan-Lun Cheng, Wen-Hsing Hsieh, Wen-Yuan Chen, Zhi-Qiang Wu
  • Patent number: 12115967
    Abstract: The disclosure provides a power control device, which comprises a bleeder circuit forming a first discharging path and an aux low-voltage (LV) power supply unit forming a second discharging path. The bleeder circuit is connected with a voltage-regulating capacitor stably maintaining the high-voltage (HV) level from a HV battery. The aux LV power supply unit is connected with the bleeder circuit and the voltage-regulating capacitor in parallel. The aux LV power supply unit provides an aux LV level to the driver, when the power system operates abnormally, the HV level is discharged through the first and second discharging path and/or a third discharging path formed by a driver and a motor.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: October 15, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Chiang Wu, Uma Sankar Rout, Bang-Yuan Liu, Yun-Huan Li
  • Publication number: 20240337015
    Abstract: Disclosed is an anti-deposition object for use in a vacuum environment with a main structure and a fluorine coating layer, the fluorine coating layer covers at least one surface of the main structure, the anti-deposition object contacts with a manufacturing process substance used or discharged during a manufacturing process performed by a manufacturing process equipment in the vacuum environment, the fluorine coating layer has a water droplet contact angle with the manufacturing process substance higher than that of the surface of the main structure, the fluorine coating layer has a hardness similar to or higher than that of the surface of the main structure, and the fluorine coating layer has a roughness lower than that of the surface of the main structure.
    Type: Application
    Filed: July 26, 2023
    Publication date: October 10, 2024
    Applicant: HIGHLIGHT TECH CORP.
    Inventors: CHIEN-HSUN CHEN, SHIH-YUAN SUN, MIN-JUI WU, CHIH-CHIANG FANG
  • Publication number: 20240337017
    Abstract: Disclosed is an anti-deposition object with a main structure and a fluorine coating layer, the fluorine coating layer covers at least one surface of the main structure, the anti-deposition object contacts with a substance in an environment, the fluorine coating layer has a water droplet contact angle with the substance higher than that of the surface of the main structure, the fluorine coating layer has a hardness similar to or higher than that of the surface of the main structure, and the fluorine coating layer has a roughness lower than that of the surface of the main structure.
    Type: Application
    Filed: January 5, 2024
    Publication date: October 10, 2024
    Applicant: HIGHLIGHT TECH CORP.
    Inventors: CHIEN-HSUN CHEN, SHIH-YUAN SUN, MIN-JUI WU, CHIH-CHIANG FANG
  • Publication number: 20240321757
    Abstract: A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.
    Type: Application
    Filed: June 5, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Chung-Shi Liu, Chih-Yuan Chang, Jiun-Yi Wu, Jeng-Shien Hsieh, Tin-Hao Kuo
  • Publication number: 20240297650
    Abstract: An input/output circuit (I/O circuit) includes the following elements. An input/output pad (I/O pad) has a plurality of operation mode, including an output mode, a normal input mode and a tolerance mode of an input mode. A first control circuit provides a first control signal in response to a pad voltage of the I/O pad and a supply voltage. A first P-type transistor has a first body region to receive a first control signal. A second P-type transistor has a second body region to receive the first control signal. In the input mode, when the pad voltage is lower than or equal to the supply voltage, the I/O pad operates in the normal input mode, and, when the pad voltage is higher than the supply voltage, the I/O pad operates in the tolerance mode, and voltage of the first control signal is equal to pad voltage.
    Type: Application
    Filed: March 28, 2023
    Publication date: September 5, 2024
    Inventors: Pei-Shin CHIU, Te-Chang WU, Chih-Yuan CHUNG, Wen-Ching HUANG
  • Patent number: 12074122
    Abstract: A structure includes a first via and a first conductive line embedded in a first dielectric layer and spaced apart from each other by the first dielectric layer. A first metal pattern disposed on the first via and embedded in a second dielectric layer. A first conductive via disposed on the first conductive line and embedded in the second dielectric layer. The first metal pattern and the first conductive via are spaced apart from each other and are located on a first horizontal level, and the first metal pattern has an open ring shape. A second via disposed on the first metal pattern and embedded in a third dielectric layer. An inductor structure including the first via, the first metal pattern, and the second via.
    Type: Grant
    Filed: April 16, 2023
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Chang, Jiun-Yi Wu, Chien-Hsun Lee, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 12069851
    Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 20, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chung-Yen Chou, Chih-Yuan Chen, Qinfu Zhang, Chao-Wei Lin, Chia-Yi Chu, Jen-Chieh Cheng, Jen-Kuo Wu, Huixian Lai
  • Publication number: 20240274380
    Abstract: A three-stage control mechanism of an explosion-proof switch has a rotating unit and an interconnecting unit. The rotating unit has a first drive portion and a second drive portion that are selectively operated and reciprocated. The interconnecting unit includes a retaining seat and a connecting member. A switch unit is connected to the connecting member. An intermediate sleeve is insertedly connected to the connecting member and extends into the retaining seat. An outer sleeve is tightly sleeved on an outer wall of the intermediate sleeve. The outer sleeve is in tight fit with the retaining seat. A movable cover is provided between the outer sleeve and the rotating unit. A connecting rod assembly includes a first connecting rod and a second connecting rod that are inserted in the intermediate sleeve. The first and second connecting rods are respectively driven by the first and second drive portions.
    Type: Application
    Filed: January 31, 2024
    Publication date: August 15, 2024
    Inventors: CHIH-YUAN WU, WEN-BING HSU
  • Patent number: 12062151
    Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: August 13, 2024
    Assignee: MediaTek Inc.
    Inventors: Ming-En Shih, Ping-Yuan Tsai, Yu-Cheng Tseng, Kuo-Chen Huang, Kuo-Chiang Lo, Hsin-Min Peng, Chun Hsien Wu, Pei-Kuei Tsung, Tung-Chien Chen, Yao-Sheng Wang, Cheng Lung Jen, Chih-Wei Chen, Chih-Wen Goo, Yu-Sheng Lin, Tsu Jui Hsu
  • Publication number: 20240264405
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Application
    Filed: April 16, 2024
    Publication date: August 8, 2024
    Inventors: Chao-Chang HU, Liang-Ting HO, Chen-Er HSU, Yi-Liang CHAN, Fu-Lai TSENG, Fu-Yuan WU, Chen-Chi KUO, Ying-Jen WANG, Wei-Han HSIA, Yi-Hsin TSENG, Wen-Chang LIN, Chun-Chia LIAO, Shou-Jen LIU, Chao-Chun CHANG, Yi-Chieh LIN, Shang-Yu HSU, Yu-Huai LIAO, Shih-Wei HUNG, Sin-Hong LIN, Kun-Shih LIN, Yu-Cheng LIN, Wen-Yen HUANG, Wei-Jhe SHEN, Chih-Shiang WU, Sin-Jhong SONG, Che-Hsiang CHIU, Sheng-Chang LIN
  • Patent number: 12055175
    Abstract: Floating fastener includes base including main body provided with through hole, resisting ring protruded inside through hole, seat body extended around main body and docking portion protruded from seat body, positioning member having shank inserted into through hole, head located at one end of shank outside main body, joint portion located at an opposite end of shank to move in and out of docking portion and stopper provided between joint portion and shank to abut against resisting ring, elastic member set on shank and stopped between head and resisting ring, and pad provided with inner hole which is inserted outside docking portion of base, so that pad abuts against seat body near the docking portion. The pad is made of soft material, which can achieve the purpose of absorbing the shaking and vibration of the floating fastener under the influence of external force.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: August 6, 2024
    Assignee: HANWIT PRECISION INDUSTRIES LTD.
    Inventors: Ming-De Wu, Chih-Yuan Chen
  • Patent number: 12057284
    Abstract: A switch device structure includes an assembly of a main body and an operation body. An electrical connection module and an elastic unit are mounted on the main body. The contact arm of the electrical connection module has a first member and/or a second member with variable arrangement position. According to the position or motion of the operation body, the elastic unit provides an elastic force to push the contact arm of the electrical connection module into a contacting circuit closed state or make the elastic unit separate from the contact arm to form a circuit open state. The arrangement form of the first member and/or the second member of the contact arm of the electrical connection module is variable in accordance with the specification of the switch to achieve NO mode and NC mode.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: August 6, 2024
    Assignees: SWITCHLAB INC., Switchlab (Shanghai) Co., Ltd., GAOCHENG ELECTRONICS CO., LTD.
    Inventors: Chih-Yuan Wu, Chih Kun Hsiao
  • Publication number: 20240258163
    Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 1, 2024
    Inventors: Chih-Yuan TING, Ya-Lien LEE, Chung-Wen WU, Jeng-Shiou CHEN
  • Patent number: 12040235
    Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
  • Patent number: 12038682
    Abstract: An optical system is provided and includes a fixed assembly, a movable element and a driving module. The fixed assembly has a main axis. The movable element is movable relative to the fixed assembly and coupled to a first optical element. The driving module is configured to drive the movable element to move relative to the fixed assembly. The driving module includes a first driving assembly and a second driving assembly, and the first driving assembly and the second driving assembly are individually operable.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 16, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Che-Wei Chang, Chih-Wen Chiang, Chen-Er Hsu, Fu-Yuan Wu, Shou-Jen Liu, Chih-Wei Weng, Mao-Kuo Hsu, Hsueh-Ju Lu, Che-Hsiang Chiu
  • Patent number: 12040281
    Abstract: A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Chung-Shi Liu, Chih-Yuan Chang, Jiun-Yi Wu, Jeng-Shien Hsieh, Tin-Hao Kuo
  • Patent number: D1049066
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: October 29, 2024
    Assignee: SYSKEY TECHNOLOGY CO., LTD.
    Inventors: Hsueh-Hsien Wu, Chih-Yuan Chan, Yi-Ting Lai