Patents by Inventor Chih-Yueh Li

Chih-Yueh Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210225932
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
  • Publication number: 20210151666
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 20, 2021
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11004897
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
    Type: Grant
    Filed: August 4, 2019
    Date of Patent: May 11, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
  • Publication number: 20210119115
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Application
    Filed: December 27, 2020
    Publication date: April 22, 2021
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 10916694
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Publication number: 20210005662
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
    Type: Application
    Filed: August 4, 2019
    Publication date: January 7, 2021
    Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
  • Publication number: 20200212290
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 2, 2020
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Publication number: 20200185597
    Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Kun-Ju Li, Hsin-Jung Liu, I-Ming Tseng, Chau-Chung Hou, Yu-Lung Shih, Fu-Chun Hsiao, Hui-Lin Wang, Tzu-Hsiang Hung, Chih-Yueh Li, Ang Chan, Jing-Yin Jhang
  • Patent number: 10622245
    Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.
    Type: Grant
    Filed: June 16, 2019
    Date of Patent: April 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Ying Hsieh, Chih-Jung Chen, Chien-Hung Chen, Chih-Yueh Li, Cheng-Pu Chiu, Shih-Min Lu, Yung-Sung Lin
  • Publication number: 20200057966
    Abstract: A training apparatus and a training method for providing a sample size expanding model are provided. A normalizing unit receives a training data set with at least one numeric predictor factor and a numeric response factor. An encoding unit trains the training data set in an initial encoding layer and at least one deep encoding layer. A modeling unit extracts a mean vector and a variance vector and inputting the mean vector and the variance vector together into a latent hidden layer for obtaining the sample size expanding model. A decoding unit trains the training data set in at least one deep decoding layer and a last encoding layer. A verifying unit performs a verification of the sample size expanding model according to the outputting data set. A data generating unit generates a plurality of samples via the sample size expanding model.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 20, 2020
    Inventors: Yao-Sheng Chang, Ya-Ching Cheng, Chien-Hung Chen, Chih-Yueh Li, Da-Ching Liao
  • Publication number: 20190378752
    Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.
    Type: Application
    Filed: June 16, 2019
    Publication date: December 12, 2019
    Inventors: Chi-Ying Hsieh, Chih-Jung Chen, Chien-Hung Chen, Chih-Yueh Li, Cheng-Pu Chiu, Shih-Min Lu, Yung-Sung Lin
  • Patent number: 10373861
    Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 6, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Ying Hsieh, Chih-Jung Chen, Chien-Hung Chen, Chih-Yueh Li, Cheng-Pu Chiu, Shih-Min Lu, Yung-Sung Lin
  • Patent number: 10276443
    Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chi Chen, Chih-Chung Chen, An-Chi Liu, Chih-Yueh Li, Pei-Ching Yeh, Tsung-Chieh Yang
  • Publication number: 20180226403
    Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.
    Type: Application
    Filed: February 28, 2017
    Publication date: August 9, 2018
    Inventors: Shin-Chi Chen, Chih-Chung Chen, An-Chi Liu, Chih-Yueh Li, Pei-Ching Yeh, Tsung-Chieh Yang
  • Patent number: 9748333
    Abstract: A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: August 29, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chi Chen, Chih-Yueh Li, Pei-Ching Yeh, Chih-Jen Lin
  • Patent number: 9613796
    Abstract: The wafer bevel etching apparatus of the present invention includes a wafer-protecting mask to cover parts of a wafer. A central region and a wafer bevel region surrounding the central region are defined on the wafer. The wafer-protecting mask includes a center sheltering region and at least one wafer bevel sheltering region. The center sheltering region can completely shelter the central region of the wafer, and the wafer bevel sheltering region extends from the outside edge of the center sheltering region, shelters parts of the wafer bevel region, and exposes the other parts of the wafer bevel region.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: April 4, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Heng Yu, Chih-Yueh Li
  • Patent number: 9548268
    Abstract: A semiconductor device includes an opening, a metal nitride layer, a bilayer metal layer and a conductive bulk layer. The opening is disposed in a first dielectric layer. The metal nitride layer is disposed in the opening. The bilayer metal layer is disposed on the metal nitride layer in the opening, where the bilayer metal layer includes a first metal layer and a second metal layer which is disposed on the first metal layer and has a greater metal concentration than that of the first metal layer. The conductive bulk layer is filled in the opening.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: January 17, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Chi Huang, Yung-Hung Yen, Hsin-Hsing Chen, Chih-Yueh Li, Tsun-Min Cheng
  • Publication number: 20160322299
    Abstract: A semiconductor device includes an opening, a metal nitride layer, a bilayer metal layer and a conductive bulk layer. The opening is disposed in a first dielectric layer. The metal nitride layer is disposed in the opening. The bilayer metal layer is disposed on the metal nitride layer in the opening, where the bilayer metal layer includes a first metal layer and a second metal layer which is disposed on the first metal layer and has a greater metal concentration than that of the first metal layer. The conductive bulk layer is filled in the opening.
    Type: Application
    Filed: June 4, 2015
    Publication date: November 3, 2016
    Inventors: Chun-Chi Huang, Yung-Hung Yen, Hsin-Hsing Chen, Chih-Yueh Li, Tsun-Min Cheng
  • Publication number: 20160148878
    Abstract: A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.
    Type: Application
    Filed: December 26, 2014
    Publication date: May 26, 2016
    Inventors: Shin-Chi Chen, Chih-Yueh Li, Pei-Ching Yeh, Chih-Jen Lin
  • Patent number: 9305847
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: April 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chi Chen, Chih-Yueh Li, Shui-Yen Lu, Chi-Mao Hsu, Yuan-Chi Pai, Yu-Hong Kuo, Nien-Ting Ho