Abstract: A spring chair (cushion) structure in which the spring chair (cushion) structure, elastic body, flexile rods have sufficient pliancy and, furthermore, are slanted at equal intervals apart such that they conjoin two frame members into a single structural entity. When sitting in the spring chair (cushion) structure, body weight is utilized to directly cause the torsional resiliency of the elastic body to produce an appropriate spring-loaded and buffered effect.

Abstract: A physical fitness-use trampoline structure consisting of several sufficiently flexile elastic members angularly arrayed at equal intervals apart and conjoining two frame members into a single structural entity. Given this structure, the user can, according to different positional exercise requirements, utilize the rotative twisting resiliency and differently orientated placement capabilities of the physical fitness-use trampoline for producing various physical fitness approaches and thereby achieve multiple efficacy physical fitness exercise performance.

Abstract: A spring chair (cushion) structure in which the spring chair (cushion) structure, elastic body, flexile rods have sufficient pliancy and, furthermore, are slanted at equal intervals apart such that they conjoin two frame members into a single structural entity. When sitting in the spring chair (cushion) structure, body weight is utilized to directly cause the torsional resiliency of the elastic body to produce an appropriate spring-loaded and buffered effect.

Abstract: The present invention is a method and apparatus for increasing the memory read/write speed with special function registers (SFRs). This method comprises the steps of: (1) connecting additional external memory to the processor as expanded memory, (2) mapping the address of expanded memory to the unused SFR address in the processor, and (3) creating a control flag for switching the processor between the ICE mode or the normal mode. When in the ICE mode, the processor still uses extended instructions to perform read/write with expanded memory. Switching back to the normal mode, the processor can use the internal instructions to perform read/write with expanded memory. Using this method, built-in of an internal ICE and the slowing down of read/write during debugging due to the use of an external ICE can be eliminated.

Abstract: A system chip and the related method of data access are provided. The system chip encompasses a central processing unit and a control circuit of interface. The control circuit of interface is configured for transforming an internal access address of data into one corresponded to an external temporary segment of data, so that the CPU may directly access data with the external temporary segment of data. The method of data access includes the steps of determining whether an access address of data is correspondent to an internal memory, transforming the access address into one correspondent to an external memory, and requesting data access with the external memory. The data access may be suspended prior to sending the CPU a confirmation of request while the data access may be executed with the external memory when the request is confirmed by the external memory.

Abstract: A scrambling method for generating recording data onto a disc includes vertically scrambling main data, which is stored in DRAM, to generate PO, wherein the scrambled data due to generate PO is not stored in DRAM; then scrambling data again to generate PI; the scrambled data due to generating PI adds with ID, IED, RSV, EDC, PI, and PO, arranging in orders and recording onto a disc.

Abstract: The present invention is a method and apparatus for increasing the memory read/write speed with special function registers (SFRs). This method comprises the steps of: (1) connecting additional external memory to the processor as expanded memory, (2) mapping the address of expanded memory to the unused SFR address in the processor, and (3) creating a control flag for switching the processor between the ICE mode or the normal mode. When in the ICE mode, the processor still uses extended instructions to perform read/write with expanded memory. Switching back to the normal mode, the processor can use the internal instructions to perform read/write with expanded memory. Using this method, built-in of an internal ICE and the slowing down of read/write during debugging due to the use of an external ICE can be eliminated.

Abstract: A method for debugging an electronic product using the internal I/O port and related apparatus uses an in-circuit emulator (ICE) and a switching means. The ICE is permanently installed in an electronic product and electronically connected to the internal input and output (I/O) ports and the processor in the electronic product. The switching means is used to switch the processor from the normal operation mode to the debug mode, enabling the ICE processor to take over control. A computer is connected to the electronic product through the internal I/O port. Through a special debug program executed from the computer, the switching means enables the ICE to carrying out the debugging/testing procedure or remote debugging, downloading or updating firm-ware. This method obviates the precarious connection to an external ICE or the designing of a special interface card for interconnecting the ICE.