Abstract: A semiconductor structure includes a memory cell connected to a signal line, a first voltage line for receiving a power supply voltage, and a second voltage line for receiving an electric ground voltage, a logic cell configured to provide logic function to the memory cell, a transition region extending from a first boundary of the memory cell to a second boundary of the logic cell, and an interconnect structure disposed over the memory cell and the logic cell. The interconnect structure includes the signal line, the first voltage line, and the second voltage line located in a same metal line layer of the interconnect structure. The signal line extends from inside the second boundary of the logic cell and into the first boundary of the memory cell. The transition region includes one or more functional transistors electrically coupled to the memory cell.

Abstract: A hammer tacker is provided, wherein the hammer tacker includes: a main body integrally made of plastic and including two side walls and a top wall, each side wall including an ear portion which includes a stop point, a first position and a second position between two ends of each side wall and the stop point, each side wall being gradually thicker from the first position to the stop point, from the second position to the stop point, and from the top wall to the stop point; and a striking mechanism rotatably connected to the two side walls and swingable to abut against the stop point, including a magazine and a striking member, the magazine being disposed between the two side walls and movable relative to the main body, movably located above the magazine, and being configured to strike a staple out from the magazine.

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, a second transistor in the first region, and a third transistor in the second region. The first transistor includes a first channel layer and a first gate dielectric layer on the first channel layer. The second transistor includes a second channel layer and a second gate dielectric layer on the second channel layer. The second gate dielectric layer is thicker than the first gate dielectric layer. The third transistor includes a third channel layer and a third gate dielectric layer on the third channel layer. The third gate dielectric layer is thicker than the second gate dielectric layer.

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

Abstract: A method includes providing a structure having a first channel member, a second channel member, and a third channel member, forming a first oxide layer, a second oxide layer, and a third oxide layer, the first oxide layer wrapping the first channel member, the second oxide layer wrapping the second channel member, the third oxide layer wrapping the third channel member, forming a first capping layer, a second capping layer, and a third capping layer over the first oxide layer, the second oxide layer, and the third oxide layer, respectively, removing the second capping layer, and after removing the second capping layer performing an oxide growing process to increase a thickness of the second oxide layer.

Abstract: A semiconductor structure includes a base structure, a first portion, a second portion and a first stack. The first portion and the second portion are disposed on the base structure and are respectively made of a first semiconductor material and a second semiconductor material which has a conductivity type opposite to that of the first semiconductor material. The first stack is disposed on the base structure and between the first portion and the second portion. The first stack includes a plurality of first semiconductor regions and a plurality of first dielectric regions disposed to alternate with the first semiconductor regions, such that each of the first semiconductor regions and the first dielectric regions extends between the first portion and the second portion. The first semiconductor regions has a dopant concentration which is lower than that of each of the first portion and the second portion.

Abstract: A semiconductor structure includes a base structure, at least one diode device and a semiconductor device. The base structure has a first base region and a second base region. The at least one diode device includes a first feature formed in the first base region, and a second feature formed over the first feature and having a conductivity type opposite to that of the first feature. The semiconductor device is formed on the second base region.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

Abstract: A method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. The method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

Abstract: A method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. The method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. The fin structure is cut into two segments by the trench. A first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first source/drain structure and a second source/drain structure over and in a substrate. The method includes forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack over the substrate. Each of the first gate stack or the second gate stack is wider than each of the third gate stack or the fourth gate stack. The method includes forming a first contact structure and a second contact structure over the first source/drain structure and the second source/drain structure respectively. A first average width of the first contact structure is substantially equal to a second average width of the second contact structure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a first trench in the base and between the first fin and the second fin. The method includes forming an isolation layer over the base and in the first trench. The first fin and the second fin are partially in the isolation layer. The method includes forming a first gate stack over the first fin and the isolation layer. The method includes forming a second gate stack over the second fin and the isolation layer. The method includes removing a bottom portion of the base. The isolation layer passes through the base after the bottom portion of the base is removed.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

Abstract: A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.

Abstract: A structure includes a fin on a substrate; first and second gate stacks over the fin and including first and second gate dielectric layers and first and second gate electrodes respectively; and a dielectric gate over the fin and between the first and second gate stacks. The dielectric gate includes a dielectric material layer on a third gate dielectric layer. In a cross-sectional view cut along a direction parallel to a lengthwise direction of the fin and offset from the fin, the first gate dielectric layer forms a first U shape, the third gate dielectric layer forms a second U shape, a portion of the first gate electrode is disposed within the first U shape, a portion of the dielectric material layer is disposed within the second U shape, and a portion of an interlayer dielectric layer is disposed laterally between the first and the second U shapes.

Abstract: A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.