Patents by Inventor Chihak Ahn

Chihak Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230178420
    Abstract: Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.
    Type: Application
    Filed: February 24, 2022
    Publication date: June 8, 2023
    Inventors: Ming He, JaeHyun Park, Chihak Ahn, Mehdi Saremi, Rebecca Park, Harsono Simka, Daewon Ha
  • Publication number: 20210351270
    Abstract: A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A <001> direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.
    Type: Application
    Filed: June 12, 2020
    Publication date: November 11, 2021
    Inventors: Hong-Hyun Park, Zhengping Jiang, Hesameddin Ilatikhameneh, Woosung Choi, Chihak Ahn
  • Patent number: 11171211
    Abstract: A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A <001> direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: November 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Hyun Park, Zhengping Jiang, Hesameddin Ilatikhameneh, Woosung Choi, Chihak Ahn
  • Publication number: 20190155971
    Abstract: A system and method for calculating stress in a device includes receiving an analytic solution domain and calculating initial analytic values for displacement and stress for a dislocation in the domain and creating a stress profile using the initial displacement and the initial stress as initial values of a stress equilibration equation.
    Type: Application
    Filed: January 19, 2018
    Publication date: May 23, 2019
    Inventors: Chihak Ahn, Woosung Choi