Abstract: A circuit according to the present invention includes: an oscillator; an divider; a time-to-digital converter comparing the phase and frequency of a reference clock signal REF from the divider with an internal clock signal and outputting digital data D1 based on the comparison results; a digital loop filter receiving the D1 and outputting digital data W1; a data holder holding the W1 from the filter in time series manner; a switch selecting either digital data W2 from the holder or the W1 and outputting the selected data as digital data W3; a digitally controlled oscillator with oscillation frequency controlled based on the W3; and a data controller switching input data of the switch, and starting/halting the operation of the oscillator, the divider, the converter and the filter. Current consumption by the digital PLL circuit can be reduced.