Patents by Inventor Chiharu Sakaki

Chiharu Sakaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210375841
    Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.
    Type: Application
    Filed: August 10, 2021
    Publication date: December 2, 2021
    Inventors: Koshi Himeda, Tatsuya Kitamura, Chiharu Sakaki, Shinya Kiyono, Sho Fujita, Atsushi Yamamoto, Takeshi Furukawa, Kenji Nishiyama, Tatsuya Funaki, Kinya Aoki
  • Patent number: 11121123
    Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 14, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Koshi Himeda, Tatsuya Kitamura, Chiharu Sakaki, Shinya Kiyono, Sho Fujita, Atsushi Yamamoto, Takeshi Furukawa, Kenji Nishiyama, Tatsuya Funaki, Kinya Aoki
  • Publication number: 20200321157
    Abstract: An electronic component includes a single-layer glass plate, an outer-surface conductor that is disposed above an outer surface of the single-layer glass plate and that is at least a part of an electrical element, and a terminal electrode that is a terminal of the electrical element. The terminal electrode is disposed above the outer surface of the single-layer glass plate and being electrically connected to the outer-surface conductor.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 8, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hiraku KAWAI, Noboru SHIOKAWA, Yuichi IIDA, Yoshitaka MATSUKI, Masahiro KUBOTA, Kenji NISHIYAMA, Takaya WADA, Tadashi WASHIMORI, Rikiya SANO, Chiharu SAKAKI
  • Publication number: 20200321323
    Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Koshi Himeda, Tatsuya Kitamura, Chiharu Sakaki, Shinya Kiyono, Sho Fujita, Atsushi Yamamoto, Takeshi Furukawa, Kenji Nishiyama, Tatsuya Funaki, Kinya Aoki
  • Patent number: 7965020
    Abstract: A piezoelectric ceramic which has a large value of coercive electric field and, in addition, which can be fired at low temperatures of 950° C. or lower, is provided. It has a composition represented by Pbx-a-dBiaM3d{M1b(M21/3Nb2/3)yZr1-b-y-zTiz}O3 where M1 and M2 represent, independently, at least one of Ni and Zn, and M3 represents at least one of Ba and Sr, 0.05?a?0.15, 0<b?0.075, 0?(a?2b), 0?d?0.1, 0.97?x?1.00, 0.020?y?0.250, and 0.398?z?0.512. It is preferable that M1 represents Ni, and M2 represents at least one of Ni and Zn. Moreover, it is preferable that Ni is in the state of being segregated.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: June 21, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Chiharu Sakaki, Emi Shimomura, Motoyoshi Sakai, Motonori Nakamura
  • Publication number: 20090200898
    Abstract: A piezoelectric ceramic which has a large value of coercive electric field and, in addition, which can be fired at low temperatures of 950° C. or lower, is provided. It has a composition represented by Pbx-a-dBiaM3d{M1b(M21/3Nb2/3)yZr1-b-y-zTiz}O3 where M1 and M2 represent, independently, at least one of Ni and Zn, and M3 represents at least one of Ba and Sr, 0.05?a?0.15, 0<b?0.075, 0?(a?2b), 0?d?0.1, 0.97?x?1.00, 0.020?y?0.250, and 0.398?z?0.512. It is preferable that M1 represents Ni, and M2 represents at least one of Ni and Zn. Moreover, it is preferable that Ni is in the state of being segregated.
    Type: Application
    Filed: April 20, 2009
    Publication date: August 13, 2009
    Inventors: Chiharu Sakaki, Emi Shimomura, Motoyoshi Sakai, Motonori Nakamura