Patents by Inventor Chih-Cheng Chen
Chih-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178300Abstract: A device includes a semiconductor fin semiconductor fin extending from a substrate, a gate structure extending across the semiconductor fin, and a multilayer gate spacer on a sidewall of the gate structure. The multilayer gate spacer includes an inner spacer layer, an outer spacer layer, and a dielectric structure. The inner spacer layer has a vertical portion extending along the sidewall of the gate structure, and a lateral portion laterally extending from the vertical portion in a direction away from the gate structure. The outer spacer layer is spaced apart from the vertical portion of the inner spacer layer by an air gap. The dielectric structure spaces apart a bottom end of the outer spacer layer from the lateral portion of the inner spacer layer.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Yin CHEN, Che-Cheng CHANG, Chih-Han LIN
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Publication number: 20240175635Abstract: This disclosure is directed to a liquid cooling device having at least two collecting tanks and at least one pair of heat-exchange plates. The tanks are separated from each other. Each of the collecting tanks has a joint tube. Each of the heat-exchange plates is in elongated shape and the collecting tanks are connected serially by the heat-exchange plates. The two collecting tanks are connected by the pair of heat-exchange plates. Each of the heat-exchange plates has a channel extended along the longitudinal direction thereof. The channels in the heat-exchange plates are connected to the collecting tanks at two ends of the heat-exchange plates, respectively. The longitudinal directions of the channels of the heat-exchange plates between the collecting tanks are parallel to each other.Type: ApplicationFiled: November 27, 2023Publication date: May 30, 2024Inventors: Kuan-Cheng LU, Chih-Hao HSIA, Wei-Fang WU, Meng-Yu CHEN
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Patent number: 11996772Abstract: The present invention provides a voltage control method for controlling a power supply. The voltage control method comprises the following steps: obtaining a present output voltage value associated with a present gain value; obtaining a predetermined output voltage value associated with a predetermined duty ratio; calculating a target gain value, corresponding to the predetermined duty ratio, according to a gain value formula; performing a weight calculation on the present gain value and the target gain value for generating a buffer gain value; and setting an output voltage command according to the buffer gain value. Wherein the buffer gain value is between the present gain value and the target gain value.Type: GrantFiled: December 27, 2021Date of Patent: May 28, 2024Assignee: Chroma ATE Inc.Inventors: Szu-Chieh Su, Wei-Chin Tseng, Chih-Hsien Wang, His-Ping Tsai, Wen-Chih Chen, Guei-Cheng Hu
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Patent number: 11997798Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.Type: GrantFiled: August 30, 2022Date of Patent: May 28, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wu Chou Hsu, Hsing Kuo Tien, Chih-Cheng Lee, Min-Yao Chen
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Patent number: 11995471Abstract: A resource integration method includes the following steps: a receiving module receives access information from a guest operating system on the host device; the access information is used to determine whether the frame rate is lower than a frame rate threshold; when the receiving module determines that the frame rate is lower than the frame rate threshold, the receiving module transmits an external resource request signal to the receiving module; after the receiving module receives the external resource request signal, a resource management module (which is located in the bridge module) selects an optimal external device from a specific category (among a plurality of categories in a candidate list), and a calculation operation or a storage operation corresponding to the specific category is transmitted to the optimal external device for calculation or storage by the bridge module.Type: GrantFiled: May 19, 2021Date of Patent: May 28, 2024Assignee: ACER INCORPORATEDInventors: Kuan-Ju Chen, Wen-Cheng Hsu, Hung-Ming Chang, Chih-Wen Huang, Chao-Kuang Yang
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Patent number: 11996483Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.Type: GrantFiled: December 14, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
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Publication number: 20240170543Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
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Publication number: 20240170336Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
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Patent number: 11990471Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.Type: GrantFiled: August 10, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
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Publication number: 20240162227Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.Type: ApplicationFiled: November 19, 2023Publication date: May 16, 2024Inventors: Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG, Kuan-Lun CHENG
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Patent number: 11984488Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.Type: GrantFiled: April 30, 2021Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng
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Patent number: 11984363Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial feature having a first semiconductor material over the semiconductor substrate, and a second epitaxial feature having a second semiconductor material over the semiconductor substrate. The second semiconductor material being different from the first semiconductor material. The semiconductor device further includes a first silicide layer on the first epitaxial feature, a second silicide layer on the second epitaxial feature, a metal layer on the first silicide layer, a first contact feature over the metal layer, and a second contact feature over the second silicide layer. A first number of layers between the first contact feature and the first epitaxial feature is greater than a second number of layers between the second contact feature and the second epitaxial feature.Type: GrantFiled: November 28, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
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Patent number: 11982936Abstract: A method of fabricating a photomask includes selectively exposing portions of a photomask blank to radiation to change an optical property of the portions of the photomask blank exposed to the radiation, thereby forming a pattern of exposed portions of the photomask blank and unexposed portions of the photomask blank. The pattern corresponds to a pattern of semiconductor device features.Type: GrantFiled: June 30, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chang Lee, Ping-Hsun Lin, Yen-Cheng Ho, Chih-Cheng Lin, Chia-Jen Chen
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Patent number: 11985324Abstract: Exemplary video processing methods and apparatuses for encoding or decoding a current block by inter prediction are disclosed. Input data of a current block is received and partitioned into sub-partitions and motion refinement is independently performed on each sub-partition. A reference block for each sub-partition is obtained from one or more reference pictures according to an initial motion vector (MV). A refined MV for each sub-partition is derived by searching around the initial MV with N-pixel refinement. One or more boundary pixels of the reference block for a sub-partition is padded for motion compensation of the sub-partition. A final predictor for the current block is generated by performing motion compensation for each sub-partition according to its refined MV. The current block is then encoded or decoded according to the final predictor.Type: GrantFiled: March 13, 2020Date of Patent: May 14, 2024Assignee: HFI INNOVATION INC.Inventors: Yu-Cheng Lin, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
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Publication number: 20240154025Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metalType: ApplicationFiled: January 10, 2024Publication date: May 9, 2024Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
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Publication number: 20240154043Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.Type: ApplicationFiled: January 2, 2024Publication date: May 9, 2024Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240153958Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.Type: ApplicationFiled: January 7, 2024Publication date: May 9, 2024Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
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Patent number: 11978677Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.Type: GrantFiled: August 27, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240146085Abstract: The present disclosure provides a battery charging system and method. The battery charging method includes: determining a degree of healthy of a battery module according to an evaluation mechanism; setting a charging standard according to the degree of healthy; by handshaking with a charger, setting a charging voltage for the charger according to the charging standard to charge the battery module; and by the charger, perform a charging operation on the battery module until a fully charged condition is satisfied.Type: ApplicationFiled: October 31, 2023Publication date: May 2, 2024Inventors: Tsung-Nan WU, Chih-Hsiang HSU, Wei-Cheng CHEN
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Publication number: 20240145540Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.Type: ApplicationFiled: January 20, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Guan-Lin CHEN, Jung-Chien CHENG, Chih-Hao WANG