Patents by Inventor Chihiro Arai
Chihiro Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060097351Abstract: A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in a collector region 13 is formed on the surface of the semiconductor substrate 1; and a base semiconductor layer 14B is formed in contact with the collector region through the first opening 51. The base semiconductor layer 14B is formed such that the edge thereof extends onto the first insulating layer 31.Type: ApplicationFiled: December 15, 2005Publication date: May 11, 2006Inventor: Chihiro Arai
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Publication number: 20040235256Abstract: A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in a collector region 13 is formed on the surface of the semiconductor substrate 1; and a base semiconductor layer 14B is formed in contact with the collector region through the first opening 51. The base semiconductor layer 14B is formed such that the edge thereof extends onto the first insulating layer 31.Type: ApplicationFiled: February 24, 2004Publication date: November 25, 2004Inventor: Chihiro Arai
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Patent number: 6798001Abstract: A semiconductor device having a photo diode which has substantially the same sensitivity to a plurality of light having different wavelengths, includes a first and a second conductivity type semiconductor layer formed at a surface layer portion of the first conductivity type semiconductor layer, wherein the sensitivity to light of a first wavelength and a second wavelength which is different from the first wavelength, are made substantially the same by designing a region in which a depletion layer spreads from a junction of the first and second conductivity type semiconductor layers and when an inverse bias is applied to the first and second conductivity type semiconductor layers, for example, by designing it to spread in a region of 3 to 6 &mgr;m or a region of 2 to 7 &mgr;m from the surface of the second conductivity type semiconductor layer in the depth direction.Type: GrantFiled: July 10, 2001Date of Patent: September 28, 2004Assignee: Sony CorporationInventors: Tomotaka Fujisawa, Chihiro Arai
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Patent number: 6756280Abstract: In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.Type: GrantFiled: May 21, 2003Date of Patent: June 29, 2004Assignee: Sony CoporationInventors: Tomotaka Fujisawa, Chihiro Arai
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Patent number: 6730557Abstract: A semiconductor device having a bipolar transistor which is capable of high integration, and a semiconductor device in which the bipolar transistor has good characteristic properties. A process for producing said semiconductor device.Type: GrantFiled: July 10, 2001Date of Patent: May 4, 2004Assignee: Sony CorporationInventor: Chihiro Arai
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Publication number: 20030205735Abstract: In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.Type: ApplicationFiled: May 21, 2003Publication date: November 6, 2003Inventors: Tomotaka Fujisawa, Chihiro Arai
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Patent number: 6642605Abstract: In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.Type: GrantFiled: June 4, 2002Date of Patent: November 4, 2003Assignee: Sony CorporationInventors: Tomotaka Fujisawa, Chihiro Arai
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Publication number: 20030116821Abstract: In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.Type: ApplicationFiled: June 4, 2002Publication date: June 26, 2003Inventors: Tomotaka Fujisawa, Chihiro Arai
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Patent number: 6445057Abstract: In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.Type: GrantFiled: January 18, 2000Date of Patent: September 3, 2002Assignee: Sony CorporationInventors: Tomotaka Fujisawa, Chihiro Arai
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Patent number: 6380602Abstract: A semiconductor device in which a photoreceptor element and a semiconductor element are formed on a common semiconductor substrate, includes: a substrate of a first conductive type; and a semiconductor layer of a second conductive type formed on the substrate; wherein the photoreceptor element is composed of the substrate and the semiconductor layer; and an impurity concentration region of the first conductive type having an impurity concentration higher than that of the substrate is provided at a position under the semiconductor layer in a region where the semiconductor element is to be formed.Type: GrantFiled: April 25, 2000Date of Patent: April 30, 2002Assignee: Sony CorporationInventors: Tomotaka Fujisawa, Chihiro Arai
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Publication number: 20020048873Abstract: A semiconductor device having a bipolar transistor which is capable of high integration, and a semiconductor device in which the bipolar transistor has good characteristic properties. A process for producing said semiconductor device.Type: ApplicationFiled: July 10, 2001Publication date: April 25, 2002Inventor: Chihiro Arai
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Patent number: 6376871Abstract: A semiconductor device includes a photodetector having a junction at which a first conductive type first semiconductor portion and a second conductive type second semiconductor portion are joined to each other. In this photodetector, division regions are formed in part of the first semiconductor portion in such a manner as to cross the first semiconductor portion and partially enter the second semiconductor portion, so that the junction is divided into a plurality of parts by the division regions, to form a plurality of photodetector regions having the divided junction parts.Type: GrantFiled: August 18, 2000Date of Patent: April 23, 2002Assignee: Sony CorporationInventor: Chihiro Arai
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Publication number: 20020017655Abstract: A semiconductor device having a photo diode which has substantially the same sensitivity to a plurality of light having different wavelengths, comprising a first conductivity type semiconductor layer and a second conductivity type semiconductor layer formed at a surface layer portion of said first conductivity type semiconductor layer, wherein the sensitivity to light of a first wavelength and the sensitivity to light of a second wavelength which is different from said first wavelength are made substantially the same by designing a region in which a depletion layer spreads from a junction of said first conductivity type semiconductor layer and said second conductivity type semiconductor layer when an inverse bias is applied to said first conductivity type semiconductor layer and said second conductivity type semiconductor layer, for example, by designing it to spread in a region of 3 to 6 &mgr;m or a region of 2 to 7 &mgr;m from the surface of the second conductivity type semiconductor layer in the depth direType: ApplicationFiled: July 10, 2001Publication date: February 14, 2002Inventors: Tomotaka Fujisawa, Chihiro Arai
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Patent number: 6344384Abstract: A method of production of a semiconductor device able to be miniaturized by preventing the decline of the hfe at a low current caused by an increase of a surface recombination current of a bipolar transistor and forming the external base region by self-alignment with respect to emitter polycrystalline silicon in the BiCMOS process. An intrinsic base region of a first semiconductor element is formed, an insulating film having an opening at an emitter formation region of part of the intrinsic base region is formed, and then an emitter electrode of the first semiconductor element and a protective film are formed on an insulating film having the opening. Next, a sidewall insulating film is left on the gate electrode side portion. Simultaneously, the insulating film is removed while partially leaving the emitter region forming-use insulating film under the emitter electrode.Type: GrantFiled: May 18, 2001Date of Patent: February 5, 2002Assignee: Sony CorporationInventors: Chihiro Arai, Hiroyuki Miwa
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Publication number: 20010055845Abstract: A method of production of a semiconductor device able to be miniaturized by preventing the decline of the hFE at a low current caused by an increase of a surface recombination current of a bipolar transistor and forming an external base region by self-alignment with respect to emitter polycrystalline silicon in the BiCMOS process. An intrinsic base region of a first semiconductor element is formed, then an insulating film having an opening at an emitter formation region of part of the intrinsic base region is formed, and an emitter electrode of the first semiconductor element and a protective film are formed on an insulating film having the opening. Next, a sidewall insulating film is left on gate electrode side portion. Simultaneously, the insulating film is removed while partially leaving the emitter region forming-use insulating film under the emitter electrode.Type: ApplicationFiled: May 18, 2001Publication date: December 27, 2001Applicant: Sony CorporationInventors: Chihiro Arai, Hiroyuki Miwa
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Patent number: 6252286Abstract: When a light is irradiated on and near separated portions of a light-receiving element, a frequency characteristic grows worse. According the present invention, a light-receiving element is formed on a semiconductor substrate by a junction portion of a first conductivity-type first semiconductor portion and a second conductivity-type second semiconductor portion, i.e. p-n junction. Then, a second conductivity-type separating region is formed on a part of the first semiconductor portion. With application of a reverse-bias voltage lower than a reverse-bias voltage applied to the junction portion when the light-receiving element is driven, the first semiconductor portion is separated into a plurality of portions by a spread of a depletion layer from the junction portion comprising the light-receiving element and the junction portion comprised of the separating region, whereby the frequency characteristic is improved.Type: GrantFiled: March 9, 1999Date of Patent: June 26, 2001Assignee: Sony CorporationInventor: Chihiro Arai
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Patent number: 6184100Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N+ type diffusion layer, N− type epitaxial layer, P− type epitaxial layer, P+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P− epitaxial layer, the efficiency in density control at the time of P− type epitaxial growth can be improved.Type: GrantFiled: June 13, 1997Date of Patent: February 6, 2001Assignee: Sony CorporationInventor: Chihiro Arai
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Patent number: 5770872Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N.sup.+ type diffusion layer, N.sup.- type epitaxial layer, P.sup.- type epitaxial layer, P.sup.+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P.sup.- epitaxial layer, the efficiency in density control at the time of P.sup.- type epitaxial growth can be improved.Type: GrantFiled: December 5, 1996Date of Patent: June 23, 1998Inventor: Chihiro Arai