Patents by Inventor Chihiro Imamura

Chihiro Imamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230420573
    Abstract: A gate insulating layer of a thin film transistor includes a first gate insulating coating including an organic polymer compound or an organic-inorganic composite material, and a second gate insulating coating including one selected from a group of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The second gate insulating coating is sandwiched between the first gate insulating coating and a semiconductor layer. The first gate insulating coating has a thickness of 100 nm or greater and 1500 nm or less, and a product of the thickness and Young's modulus of the first gate insulating coating is 300 nm·GPa or greater and 30000 nm·GPa or less. The second gate insulating coating has a thickness of 2 nm or greater and 30 nm or less, and a product of the thickness and Young's modulus of the second gate insulating coating is 100 nm·GPa or greater and 9000 nm·GPa or less.
    Type: Application
    Filed: September 13, 2023
    Publication date: December 28, 2023
    Applicant: TOPPAN Inc.
    Inventors: Chihiro IMAMURA, Manabu ITO
  • Publication number: 20230387242
    Abstract: A gate insulating layer includes a first gate insulating film including an organic polymer compound and covering a second part of a support surface and a gate electrode layer, and second gate insulating film including an inorganic silicon compound and sandwiched between the first gate insulating film and a semiconductor layer. The second gate insulating film has a thickness of 2 nm or greater and 30 nm or less, and the second gate insulating film has a hydrogen content of 5 at % or more and 13 at % or less so as to enhance the electrical durability of the thin film transistor against bending of the flexible substrate.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Applicant: TOPPAN Inc.
    Inventors: Chihiro IMAMURA, Manabu ITO, Yukikazu TANAKA
  • Patent number: 9589997
    Abstract: Since the gate electrode (1) and the capacitor electrode (2) are made into a double layer structure, the first layers (1a, 2a) in contact with the substrate (0) are made of ITO, and the second layers (1b, 2b) in contact with the gate insulating layer (3) are made of an metallic oxide layer, it becomes possible to form the gate electrode (1) and the capacitor electrode (2) having high optical transparency and high conductivity. Therefore, it becomes possible to improve the optical transparency of a thin film transistor and to improve the display performance of an image displaying apparatus for which the thin film transistor is used by using the above-described gate electrode (1) and the above-described capacitor electrode (2).
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: March 7, 2017
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Chihiro Imamura, Manabu Ito
  • Patent number: 8963147
    Abstract: A thin film transistor includes, on an insulating substrate, at least: a gate electrode; a gate insulating layer; a source electrode; a drain electrode; a metal oxide layer including a semiconductor region and an insulating region, each of the semiconductor region and the insulating region being composed of a same metal oxide material; and an insulating protective layer. The semiconductor region includes a region between the source electrode and the drain electrode, and is overlaid on a part of each of them. The semiconductor region is formed between the gate insulating layer and the insulating protective layer to abut on at least one of them. The electric conductivity of the semiconductor region is higher than that of the insulating region.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 24, 2015
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Chihiro Imamura, Yukari Miyairi, Hiroaki Koyama
  • Patent number: 8848124
    Abstract: According to the first aspect of the present invention, a drain electrode and a pixel electrode are electrically connected to each other on a protective film formed on a semiconductor active layer, and thereby it is possible to easily connect the drain electrode and the pixel electrode to each other and to improve a yield.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: September 30, 2014
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Noriaki Ikeda, Chihiro Imamura, Manabu Ito
  • Publication number: 20140246675
    Abstract: Since the gate electrode (1) and the capacitor electrode (2) are made into a double layer structure, the first layers (1a, 2a) in contact with the substrate (0) are made of ITO, and the second layers (1b, 2b) in contact with the gate insulating layer (3) are made of an metallic oxide layer, it becomes possible to form the gate electrode (1) and the capacitor electrode (2) having high optical transparency and high conductivity. Therefore, it becomes possible to improve the optical transparency of a thin film transistor and to improve the display performance of an image displaying apparatus for which the thin film transistor is used by using the above-described gate electrode (1) and the above-described capacitor electrode (2).
    Type: Application
    Filed: September 20, 2012
    Publication date: September 4, 2014
    Applicant: Toppan Printing Co., Ltd.
    Inventors: Chihiro Imamura, Manabu Ito
  • Publication number: 20140217396
    Abstract: A thin film transistor includes, on an insulating substrate, at least: a gate electrode; a gate insulating layer; a source electrode; a drain electrode; a metal oxide layer including a semiconductor region and an insulating region, each of the semiconductor region and the insulating region being composed of a same metal oxide material; and an insulating protective layer. The semiconductor region includes a region between the source electrode and the drain electrode, and is overlaid on a part of each of them. The semiconductor region is formed between the gate insulating layer and the insulating protective layer to abut on at least one of them. The electric conductivity of the semiconductor region is higher than that of the insulating region.
    Type: Application
    Filed: September 21, 2011
    Publication date: August 7, 2014
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Chihiro Imamura, Yukari Miyairi, Hiroaki Koyama
  • Publication number: 20120262642
    Abstract: According to the first aspect of the present invention, a drain electrode and a pixel electrode are electrically connected to each other on a protective film formed on a semiconductor active layer, and thereby it is possible to easily connect the drain electrode and the pixel electrode to each other and to improve a yield.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 18, 2012
    Applicant: Toppan Printing Co., Ltd.
    Inventors: Noriaki IKEDA, Chihiro Imamura, Manabu Ito