Abstract: A maintenance management system according to the present invention has an electronic device and a database server. In one embodiment of the invention, the electronic device further includes: (1) a log generating unit for collecting states of components and generating a log when a failure is detected during execution of a process; (2) a DB inquiry unit for transmitting the log to the database server and making an inquiry about whether firmware capable of solving the failure exists; and (3) an updating process unit for obtaining firmware capable of solving the failure from the database server and updating firmware in the electronic device with the obtained firmware. In addition, the database server further includes: a storing unit for storing a database having version information of firmware and failure correction information; and an inquiry responding unit for identifying when firmware for solving the failure exists.

Abstract: A maintenance management system according to the present invention has an electronic device and a database server. In one embodiment of the invention, the electronic device further includes: (1) a log generating unit for collecting states of components and generating a log when a failure is detected during execution of a process; (2) a DB inquiry unit for transmitting the log to the database server and making an inquiry about whether firmware capable of solving the failure exists; and (3) an updating process unit for obtaining firmware capable of solving the failure from the database server and updating firmware in the electronic device with the obtained firmware. In addition, the database server further includes: a storing unit for storing a database having version information of firmware and failure correction information; and an inquiry responding unit for identifying when firmware for solving the failure exists.

Abstract: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

Abstract: An input display device, including: a display area that displays a plurality of input keys; and a display controller that controls display of the plurality of input keys displayed in the display area. The display controller includes: a combination data creating portion that creates combination data of a first input key and a second input key which has been selected next to the first input key; a storage portion that stores the combination data in a memory; a candidate key extracting portion that extracts the second input key from the memory on the basis of the combination data stored in the memory when the first input key displayed on the display area is selected; and a display portion that allows the display area to display the second input key extracted by the candidate key extracting portion as a candidate which is to be selected next.

Abstract: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

Abstract: The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.

Abstract: The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.

Abstract: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

Abstract: A circuit from which a buffer and an inverter are removed without changing logic is displayed. Such a circuit is obtained by a first or a second method. With the first method, all buffers which do not change logic and, when a clock path is divided at a branch point of wiring, all pairs of inverters located on each divided clock path are removed from the clock circuit. With the second method, a logic element located on a plurality of clock paths is copied and added to the clock circuit, all buffers which do not change logic and all pairs of inverters located between logic elements other than the above buffers are removed, and redundant partial circuits, if any, realizing the same logic and being located on a plurality of clock paths are removed. Thus, the clock circuit can be displayed so as to facilitate a designer's understanding of logic.

Abstract: The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.

Abstract: A pharmaceutical composition for the treatment of peptic ulcer which contains 2-N-methyl-1,2,3,4-tetrahydro-9H-dibenzo-[a,e]-pyridino[3,4-c]cycloheptatr iene (MO-8282) or its pharmaceutically acceptable salt as an active ingredient in association with a pharmaceutically acceptable carrier, and a method for treating peptic ulcer by administering the said compound, MO-8282. The said compound exhibits high efficacy in the treatment of peptic ulcer and has low toxicity.