Patents by Inventor Chihiro SHIMAYA

Chihiro SHIMAYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Preform for semiconductor encapsulation
    Patent number: 10629506
    Abstract: Disclosed is a preform for semiconductor encapsulation, mainly containing a metal or alloy, the metal or alloy further containing Sn or Sn alloy, and, Cu or Cu alloy, and still further containing at least 2% by weight of an intermetallic compound of Cu and Sn.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 21, 2020
    Assignee: Napra Co., Ltd.
    Inventors: Shigenobu Sekine, Chihiro Shimaya
  • PREFORM FOR SEMICONDUCTOR ENCAPSULATION
    Publication number: 20180218954
    Abstract: Disclosed is a preform for semiconductor encapsulation, mainly containing a metal or alloy, the metal or alloy further containing Sn or Sn alloy, and, Cu or Cu alloy, and still further containing at least 2% by weight of an intermetallic compound of Cu and Sn.
    Type: Application
    Filed: June 22, 2017
    Publication date: August 2, 2018
    Inventors: Shigenobu SEKINE, Chihiro SHIMAYA
  • Multi-layer preform sheet
    Patent number: 9950496
    Abstract: A multi-layer preform sheet having at least a first layer and a second layer, the first layer being composed of a solder material that contains an intermetallic compound, and the second layer containing a first metal having a melting point of 300° C. or above, and a second metal capable of forming an intermetallic compound with the first metal.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: April 24, 2018
    Assignee: Napra Co., Ltd.
    Inventors: Shigenobu Sekine, Chihiro Shimaya
  • MULTI-LAYER PREFORM SHEET
    Publication number: 20180009194
    Abstract: PROBLEM: To provide a multi-layer preform sheet capable of forming a highly reliable and high-quality electric interconnect, an electro-conductive bonding portion and so forth that are less likely to produce the Kirkendall void. SOLUTION: A multi-layer preform sheet having at least a first layer and a second layer, the first layer being composed of a solder material that contains an intermetallic compound, and the second layer containing a first metal having a melting point of 300° C. or above, and a second metal capable of forming an intermetallic compound with the first metal.
    Type: Application
    Filed: November 3, 2016
    Publication date: January 11, 2018
    Inventors: Shigenobu SEKINE, Chihiro SHIMAYA