Patents by Inventor Chihiro Shin

Chihiro Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230410763
    Abstract: A driver includes a first driving circuit and a second driving circuit. The second driving circuit includes a computation amplifier, an output capacitor, a first feedback capacitor, and a second feedback capacitor. The computation amplifier is composed of a transistor with a breakdown voltage lower than the breakdown voltage of a transistor making up the first driving circuit. The output capacitor is disposed between an output node of the computation amplifier and the signal supply line. The first feedback capacitor is disposed between an inverting input node of the computation amplifier and the signal supply line. One end of the second feedback capacitor is coupled to the inverting input node of the computation amplifier.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 21, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Akira MORITA, Chihiro Shin
  • Publication number: 20230317025
    Abstract: A driver includes a data voltage output terminal electrically coupled to a data line through a data line switch of an electro-optical panel, a capacitor driving circuit configured to output first to nth capacitor driving voltages corresponding to gradation data to first to nth capacitor driving nodes, a capacitor circuit including first to nth capacitors provided between an output node and the first to nth capacitor driving nodes, a processing circuit configured to calculate an excess/deficient charge amount of the output node when the data line switch is turned on, and a charge compensation circuit configured to inject into the output node or discharge from the output node a compensation charge based on the excess/deficient charge amount calculated by the processing circuit, by using a charge compensation capacitor circuit.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 5, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Akira MORITA, Chihiro SHIN
  • Patent number: 8576257
    Abstract: An integrated circuit device includes first to Nth memory blocks disposed along a first direction, a power supply circuit, and a data driver disposed in a second direction with respect to the first to Nth memory blocks. The power supply circuit includes an analog reference power supply voltage output circuit that outputs an analog reference power supply voltage. The analog reference power supply voltage output circuit is disposed between an Mth memory block and an (M+1)th memory block among the first to Nth memory blocks. An analog reference power supply line is provided in an area of the data driver along the first direction.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: November 5, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Hiroshi Kiya, Chihiro Shin, Haruo Kamijo, Motoaki Nishimura, Katsuhiko Maki
  • Publication number: 20090160881
    Abstract: An integrated circuit device includes first to Nth memory blocks that are disposed along a first direction, and first to Nth data driver blocks that are disposed along the first direction in a second direction with respect to the first to Nth memory blocks. A Jth memory block among the first to Nth memory blocks dot-sequentially reads subpixel image data and outputs the subpixel image data to a corresponding Jth data driver block among the first to Nth data driver blocks, the subpixel image data being image data corresponding to at least one subpixel. The Jth data driver block receives the subpixel image data from the Jth memory block, and outputs a data signal corresponding to the subpixel image data.
    Type: Application
    Filed: December 19, 2008
    Publication date: June 25, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroshi KIYA, Chihiro SHIN, Haruo KAMIJO, Motoaki NISHIMURA, Katsuhiko MAKI
  • Publication number: 20090160882
    Abstract: An integrated circuit device includes first to Nth memory blocks disposed along a first direction, a power supply circuit, and a data driver disposed in a second direction with respect to the first to Nth memory blocks. The power supply circuit includes an analog reference power supply voltage output circuit that outputs an analog reference power supply voltage. The analog reference power supply voltage output circuit is disposed between an Mth memory block and an (M+1)th memory block among the first to Nth memory blocks.
    Type: Application
    Filed: December 19, 2008
    Publication date: June 25, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroshi KIYA, Chihiro SHIN, Haruo KAMIJO, Motoaki NISHIMURA, Katsuhiko MAKI
  • Publication number: 20090160849
    Abstract: An integrated circuit device includes first to Nth data driver blocks that are disposed along a first direction. Each of the first to Nth data driver blocks includes first to Mth sub-driver blocks. Each of the sub-driver blocks includes a D/A conversion circuit that receives image data and D/A-converts the image data, and first to Lth data line driver circuits that are disposed along the first direction in a second direction with respect to the D/A conversion circuit and share the D/A conversion circuit.
    Type: Application
    Filed: December 19, 2008
    Publication date: June 25, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroshi KIYA, Chihiro SHIN, Haruo KAMIJO, Motoaki NISHIMURA, Katsuhiko MAKI
  • Publication number: 20090096818
    Abstract: A data driver includes a D/A conversion circuit, a switch circuit, and a data line driver circuit. The switch circuit includes a first switch element provided between a first voltage output node of the D/A conversion circuit and a first input node of a grayscale generation amplifier, a second switch element that is provided between a second voltage output node of the D/A conversion circuit and the first input node and is exclusively turned ON/OFF with respect to the first switch element, a third switch element provided between the first voltage output node and a second input node, and a fourth switch element that is provided between the second voltage output node and the second input node and is exclusively turned ON/OFF with respect to the third switch element.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 16, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Motoaki NISHIMURA, Chihiro SHIN, Haruo KAMIJO, Katsuhiko MAKI
  • Publication number: 20080111209
    Abstract: A semiconductor device includes: a first element isolation film that is formed by a LOCOS oxidation method on a semiconductor substrate for isolating a first element region from other regions; a second element isolation film embedded in a groove formed in the semiconductor substrate for isolating a second element region from other regions; a first semiconductor element formed in the first element region; a second semiconductor element formed in the second element region; and a resistance element formed on the first element isolation film.
    Type: Application
    Filed: October 25, 2007
    Publication date: May 15, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Chihiro Shin