Abstract: A semiconductor device in which components each serving as a basic constitutional unit are arranged in order to find a solution of an interaction model. The semiconductor device includes multiple units each of which has: a first memory cell for scoring a value indicating a state of one node of the interaction model; a second memory cell for storing an interaction coefficient indicating an interaction from another node connected to the one node; a third memory cell for storing a flag for fixing a value of the first memory cell; a first arithmetic circuit that decides a next state of the one node based on a value indicating a state of the other node and the interaction coefficient; and a second arithmetic circuit that decides whether or not to record a value indicating the next state in the first memory cell according to a value of the flag.

Abstract: An object of the present invention is to realize an example of configuration that approximately represents a state of quantum spin in a semiconductor device where components as a basic configuration unit are arrayed so as to search a ground state of Ising model. There is disclosed a semiconductor device provided with plural units each of which is equipped with a first memory cell that stores a value which represents one spin of the Ising model by three or more states, a second memory cell that stores an interaction coefficient showing interaction from another spin which exerts interaction on the one spin and a logical circuit that determines the next state of the one spin on the basis of a function having a value which represents a state of the other spin and the interaction coefficient as a constant or a variable.

Abstract: It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells.

Abstract: A semiconductor device includes a plurality of spin units individually including a memory cell configured to store values of spins in an Ising model, a memory cell configured to store an interaction coefficient from an adjacent spin that exerts an interaction on the spin, a memory cell configured to store an external magnetic field coefficient of the spin, and an interaction circuit configured to determine a subsequent state of the spin. The spin units individually include a random number generator configured to supply the random number to the plurality of the spin units and generate two-valued simulated coefficients of two values or simulated coefficients of three values in performing an interaction to determine a subsequent state of a spin of the spin units from a value of a spin from an adjacent spin unit, an interaction coefficient, and an external magnetic field coefficient.

Abstract: A semiconductor device that can simulate interactions between nodes of a large-scale interaction model and can be manufactured easily at inexpensive cost is suggested.

Abstract: A semiconductor device includes a spin array in which a plurality of memory cells are disposed in a matrix configuration, a group of a predetermined number of memory cells is collected in units of spin units, and a plurality of the spin units are disposed with an adjacency; a word line provided in correspondence with rows of the memory cells; a bit line pair provided in correspondence with columns of the memory cells; a multiword decoder configured to multiplex a word address according to an input of a multiplicity specify signal to a word line and simultaneously activate a plurality of word lines; and a bit line driver configured to subject a plurality of memory cells, of the memory cells connected to bit line pairs and arrayed in a column direction, activated by the plurality of the word lines to a write operation or a read operation.

Abstract: A semiconductor device capable of easily and properly detecting a defective element unit(s) and a quality management method for the semiconductor device are suggested. A semiconducting device simulating interactions between nodes in an interaction model is equipped with a quality management unit for managing the quality of each element unit provided corresponding to each node, wherein the quality management unit executes a specified quality test of each element unit, compares test results of the quality test with pre-given results to be obtained from the quality test, and detects a defective memory cell(s) and a defective element unit(s) based on the comparison results.

Abstract: A semiconductor device has a plurality of units, each of which includes a first memory cell that stores a value indicating a state of one node of an interaction model, a second memory cell that stores an interaction coefficient indicating an interaction from a node connected to the one node, and a third memory cell that stores a bias coefficient of the one node. Furthermore, the semiconductor device has a computing circuit that determines a value indicating a next state of the one node based on a value indicating a state of the connected node, the interaction coefficient and the bias coefficient. Also, each of the second memory cell and the third memory cell in the plurality of units includes multi-valued memory cells.

Abstract: A highly-convenient information processing system capable of obtaining a solution of a problem under conditions desired by a user and a management apparatus capable of enhancing the convenience of the information processing system are suggested.

Abstract: An object of the present invention is to realize an example of configuration that approximately represents a state of quantum spin in a semiconductor device where components as a basic configuration unit are arrayed so as to search a ground state of Ising model. There is disclosed a semiconductor device provided with plural units each of which is equipped with a first memory cell that stores a value which represents one spin of the Ising model by three or more states, a second memory cell that stores an interaction coefficient showing interaction from another spin which exerts interaction on the one spin and a logical circuit that determines the next state of the one spin on the basis of a function having a value which represents a state of the other spin and the interaction coefficient as a constant or a variable.

Abstract: In a semiconductor device in which components to be a basic configuration unit are arranged in an array shape for calculating an interaction model, a technique capable of changing a topology between the components is provided. A semiconductor device includes a plurality of units each of which includes a first memory cell for storing a value indicating a state of one node of an interaction model, a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node, and a calculation circuit for determining a value indicating a next state of the one node based on a value indicating a state of the connected node and on the interaction coefficient. In addition, the semiconductor device includes a plurality of switches for connecting or disconnecting the plurality of units to/from each other.

Abstract: A semiconductor device in which components each serving as a basic constitutional unit are arranged in order to find a solution of an interaction model. The semiconductor device includes multiple units each of which has: a first memory cell for scoring a value indicating a state of one node of the interaction model; a second memory cell for storing an interaction coefficient indicating an interaction from another node connected to the one node; a third memory cell for storing a flag for fixing a value of the first memory cell; a first arithmetic circuit that decides a next state of the one node based on a value indicating a state of the other node and the interaction coefficient; and a second arithmetic circuit that decides whether or not to record a value indicating the next state in the first memory cell according to a value of the flag.

Abstract: An object of the invention is to provide a simulation system and a simulation method which are capable of efficiently presenting a simulation result which is valuable to a user. The invention achieves the above-mentioned object by performing simulation, displaying a plurality of simulation results as samples, receiving an input of information on a user's evaluation with respect to each of the displayed results by a user interface, and outputting a group of simulation results on the basis of the input information.

Abstract: An information processing unit and information processing method capable of performing a ground-state search of an Ising model having coefficients of arbitrary values regardless of restrictions on hardware or software is suggested. When a ground state of an original problem, which is an Ising model, or an approximate solution of that ground state is calculated as a solution of the original problem, one or more sub-problems which are Ising models are generated from the original problem and the information processing unit searches the ground state of each generated sub-problem and generates a solution of the original problem based on a solution of each sub-problem obtained from the search; and when types of coefficient values of an Ising model whose ground state can be searched are limited, sub-problems which are Ising models composed of the types of limited values of coefficients are generated.

Abstract: To make it possible for multiple blades to share an SR-IOV device in the form that enables a hypervisor to acquire necessary information and to make a setting between itself and a PF. A computer system has multiple servers, an I/O device, an I/O switch for connecting these servers and the I/O device, and an I/O controller for managing the I/O switch, wherein the I/O device has one or more PF's, the I/O controller has a master PF driver for accessing the PF of the I/O device, the servers have respective slave PF drivers, these slave PF drivers transfer their requests to the master PF driver in order to use the PF of the I/O device, and the master PF driver accesses the PF of the I/O device as a proxy of the slave PF driver.

Abstract: In order to improve throughput by suppressing contention of hardware resources in a computer to which a data transfer unit is coupled, a control unit for transferring data between a first interface coupled to the computer and a second interface coupled to a memory transaction issuing unit for issuing, when one of the first interface and the second interface receives an access request to a memory of the computer, a memory transaction for the main memory to the first interface, the first interface includes a plurality of interfaces coupled in parallel to the computer, and the control unit further includes a memory transaction distribution unit for extracting an address of the main memory, which is contained in the memory transaction issued by the memory transaction issuing unit, and selecting an interface having address designation information set therein, which corresponds to the extracted address to transmit the memory transaction.