Patents by Inventor Chihiro Yoshino

Chihiro Yoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080029809
    Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer on a major surface thereof. The semiconductor layer is formed to extend in the vertical direction of the major surface of the semiconductor substrate. A stress application layer is provided on either side of the semiconductor layer and applies a stress to the semiconductor layer.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 7, 2008
    Inventors: Jun Morioka, Shinichi Taka, Kiminori Watanabe, Koji Yonemura, Chihiro Yoshino, Keita Takahashi
  • Patent number: 6633069
    Abstract: A bipolar transistor has metal silicide as a base lead-out electrode instead of conventional polysilicon, and the metal silicide film extends to an edge of an etching stopper layer, to reduce an emitter resistance and restrain an occurrence of an emitter plug effect. Such bipolar transistor can be utilized in a CMOS semiconductor device.
    Type: Grant
    Filed: May 20, 1998
    Date of Patent: October 14, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Nii, Chihiro Yoshino
  • Publication number: 20020149062
    Abstract: A bipolar transistor has metal silicide as a base lead-out electrode instead of conventional polysilicon, and the metal silicide film extends to an edge of an etching stopper layer, to reduce an emitter resistance and restrain an occurrence of an emitter plug effect. Such bipolar transistor can be utilized in a CMOS semiconductor device.
    Type: Application
    Filed: May 20, 1998
    Publication date: October 17, 2002
    Inventors: HIDEAKI NII, CHIHIRO YOSHINO
  • Patent number: 6153488
    Abstract: A method for producing a semiconductor device including a bipolar transistor, has the steps of: forming an element isolating region in a major surface of a semiconductor substrate to define an element forming region to form a collector region in the element forming region surrounded by the element isolating region; allowing the epitaxial growth of a semiconductor layer on the major surface of the semiconductor substrate to form a base region of the semiconductor layer on the collector region; forming a growth inhibiting film on a region forming the base region of the semiconductor layer; removing the growth inhibiting film to expose a part of the semiconductor layer; covering the upper surface and side wall of the conductive film, which is exposed in the predetermined region, with an insulator film; covering the side wall of the conductive film, which is exposed in the predetermined region; and forming an emitter region in a surface region of the predetermined region of the semiconductor layer, which is surro
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: November 28, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Chihiro Yoshino
  • Patent number: 5886395
    Abstract: To obtain both the highest possible maximum operating frequency f.sub.max and early voltage V.sub.A, a semiconductor device provided with a bipolar transistor including a collector region, a base region formed on the collector region, an emitter region formed in contact with the base region, a base leading electrode connected to the base region, and an emitter electrode connected to the emitter region, is characterized in that a ratio Q.sub.B /N.sub.c of base Gunmel number Q.sub.B to impurity concentration N.sub.C of the collector region of the bipolar transistor lies within a range from 0.2.times.10.sup.-3 cm to 2.5.times..sup.-3 cm.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: March 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Katsumata, Chihiro Yoshino, Kazumi Inoh
  • Patent number: 5620908
    Abstract: A method of manufacturing a semiconductor device including selectively forming an element-isolating insulating layer on a surface of a semiconductor substrate to define active regions; forming a first insulating layer and removing respective portions thereof on surfaces of a second conductive type active region and a first active region of a first conductive type; oxidizing to form a gate oxide layer; forming and patterning a conductive layer to form a gate electrodes of MOS transistors and a base-extracting electrode of a bipolar transistor; forming an opening, in the base-extracting electrode, and a side wall insulating layer on an inner wall of the opening; removing first and second portions of the insulating layer to form an overhung portion; epitaxially growing a second conductive type semiconductor layer using the base-extracting electrode and active region of the first conductive type as a seed crystal; and selectively forming a first conductive type semiconductor layer that is to become an emitter tha
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: April 15, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumi Inoh, Yasuhiro Katsumata, Satoshi Matsuda, Chihiro Yoshino