Abstract: In a computer system, a method for an area based place and route of an integrated circuit layout that provides automatic iterative area placement of module cells intelligently and effectively. In one embodiment, this is accomplished in three phases. The searching phase determines which hot spot is to be refined based on a congestion map. Next, the refining phase chooses a box with the proper aspect ratio, cut line direction, and placement options for minimizing the hot spot. The scheduling phase then decides whether to proceed with another area placement based on the current result or to restore a previous placement that exhibited superior characteristics. In the course of the area placements, several parameters are randomly varied in an intelligent manner so that successive iterative area placements produce equivalent or better results. All of this is accomplished without human intervention or expert knowledge. Instead, the computer system continuously runs its program until a design goal is attained.

Abstract: A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix.

Abstract: Hierarchical look-ahead congestion-driven placement is a look-ahead method for avoiding interconnect congestion. It balances the available routing resources. When incorporated into conventional quadratic programming approaches, only minor increases in run-time are needed to produce dramatic decreases in congestion. The macrocell densities are traded between adjacent regions to anticipate congestion, and are estimated based on the current iteration for the distribution of cells and net connections involved. The congestion estimation also takes routing detour due to the presence of large hard macros into account for accuracy. The macrocell density adjustments are propagated to all the neighboring regions at each hierarchical level to revise the prior congestion estimate from the previous hierarchical iteration.