Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A sensor is provided. A first terminal of a first current source and a first terminal of a first transistor are connected to a cathode of the photodiode. A control terminal of a second transistor is connected to an output terminal of a first operational amplifier. A first terminal of the second transistor is connected to a second terminal of the first transistor through a first current mirror circuit. A second terminal of the second transistor is connected to a second current source, a second input terminal of a second operational amplifier and a first terminal of a third transistor. A first input terminal of the second operational amplifier is connected to the first terminal of the first transistor. A control terminal of the third transistor is connected to an output terminal of the second operational amplifier.

Abstract: A switching charger for supplying stable power is provided. First input terminals of first and fourth operational amplifiers and a second input terminal of a second operational amplifier are connected to a battery. A second input terminal of the first operational amplifier is coupled to a reference voltage. A first input terminal of the second operational amplifier and a second input terminal of the fourth operational amplifier are connected to an inductor. A first input terminal of a third operational amplifier is connected to an input power source. A second input terminal of the third operational amplifier is connected to a system circuit. A first selector circuit is connected to output terminals of the third and fourth operational amplifiers. A second selector circuit is connected to output terminals of the first and second operational amplifiers and the first selector circuit.

Abstract: Disclosed are methods and systems for a WLAN device operating on DFS channels to calibrate the PRI as well as delays between partial pulses of received radar pulses that are impaired due to channel and filtering effects. The calibrated PRI may approximate the PRI of the transmitted pulses. The calibrated delay between the partial pulses estimates the interval between two partial pulses that originally belong to the same transmitted pulse. Using the calibrated PRI and the calibrated delay between partial pulses, the WLAN device may reconstruct the original pulses from received impaired pulses even when the impaired pulses are delayed and partial pulses of the original pulses. The WLAN device may use the calibrated results to correct the shortened PW and varying PRI of the impaired pulses to restore the partial pulses to their full PW with a relatively uniform PRI, increasing the probability of detecting the radar signals.

Abstract: A switching charger having fast dynamic response for transition of a load is provided. A first terminal of a high-side switch is coupled to an input voltage. A first terminal of a low-side switch is connected to a second terminal of the high-side switch. A first terminal of an inductor is connected to a node between the first terminal of the low-side switch and the second terminal of the high-side switch. A second terminal of the inductor is connected to a first terminal of a capacitor. A constant on-time circuit determines a duty cycle of an on-time signal according to the input voltage and an output voltage of a node between the second terminal of the inductor and the first terminal of the capacitor. A control circuit controls a driver circuit to drive the high-side switch and the low-side switch according to the on-time signal.

Abstract: A power saving system of a battery charger is provided. A control terminal of a first transistor receives a wake-up signal. A counter is connected to a first terminal of the first transistor. The counter determines whether or not a working period of the wake-up signal from the first transistor is larger than a time threshold to output a counting signal. When the counting signal indicates that the working period of the wake-up signal is not larger than the time threshold, the counter and electronic components of an electronic device are turned off, thereby saving power of a battery. When the counting signal indicates that the working period of the wake-up signal is larger than the time threshold, the electronic device is switched from a power saving mode to a normal operation mode. In the normal operation mode, the battery can supply power to the electronic device.

Abstract: A power saving system of a battery charger is provided. A control terminal of a first transistor receives a wake-up signal. A counter is connected to a first terminal of the first transistor. The counter determines whether or not a working period of the wake-up signal from the first transistor is larger than a time threshold to output a counting signal. When the counting signal indicates that the working period of the wake-up signal is not larger than the time threshold, the counter and electronic components of an electronic device are turned off, thereby saving power of a battery. When the counting signal indicates that the working period of the wake-up signal is larger than the time threshold, the electronic device is switched from a power saving mode to a normal operation mode. In the normal operation mode, the battery can supply power to the electronic device.

Abstract: A switching charger for accurately sensing a small current is provided. First terminals of first transistors and a second transistor are coupled to a system voltage. Second terminals of the first transistors and a first input terminal of an operational amplifier are connected to a battery. A first terminal of a third transistor is connected to a second terminal of the second transistor and a second input terminal of the operational amplifier. A control terminal of the third transistor is connected to an output terminal of the operational amplifier. A first terminal of a fourth transistor is connected to a second terminal of the third transistor. First terminals of fifth transistors are coupled to an input voltage. Control terminals of the first transistors and the fifth transistors are connected to a control circuit. First terminals of sixth transistors are respectively connected to second terminals of the fifth transistors.

Abstract: A sensor is provided. A first terminal of a first current source and a first terminal of a first transistor are connected to a cathode of the photodiode. A control terminal of a second transistor is connected to an output terminal of a first operational amplifier. A first terminal of the second transistor is connected to a second terminal of the first transistor through a first current mirror circuit. A second terminal of the second transistor is connected to a second current source, a second input terminal of a second operational amplifier and a first terminal of a third transistor. A first input terminal of the second operational amplifier is connected to the first terminal of the first transistor. A control terminal of the third transistor is connected to an output terminal of the second operational amplifier.

Abstract: A sensor is provided. A first terminal of a first current source and a first terminal of a first transistor are connected to a cathode of the photodiode. A control terminal of a second transistor is connected to an output terminal of a first operational amplifier. A first terminal of the second transistor is connected to a second terminal of the first transistor through a first current mirror circuit. A second terminal of the second transistor is connected to a second current source, a second input terminal of a second operational amplifier and a first terminal of a third transistor. A first input terminal of the second operational amplifier is connected to the first terminal of the first transistor. A control terminal of the third transistor is connected to an output terminal of the second operational amplifier.

Abstract: A sensor is provided. A first terminal of a first current source and a first terminal of a first transistor are connected to a cathode of the photodiode. A control terminal of a second transistor is connected to an output terminal of a first operational amplifier. A first terminal of the second transistor is connected to a second terminal of the first transistor through a first current mirror circuit. A second terminal of the second transistor is connected to a second current source, a second input terminal of a second operational amplifier and a first terminal of a third transistor. A first input terminal of the second operational amplifier is connected to the first terminal of the first transistor. A control terminal of the third transistor is connected to an output terminal of the second operational amplifier.

Abstract: A light sensing device is provided, which includes a photodiode, a capacitor circuit and an ADC. The ADC includes a comparator, a counter, a reset switch, a logic circuit and a reference voltage switching circuit. The reference voltage switching circuit is controlled by the logic circuit to a determination reference voltage. When a primary integration time ends, a first node has a residual voltage that does not reach a reference voltage, the logic circuit controls the reference voltage switching circuit to provide the determination reference voltage to the comparator or the capacitor circuit within a secondary integration time, and the comparator outputs a comparison signal, the logic circuit receives the comparison signal within the secondary integration time, and determines the secondary value and outputs to the counter. The counter generates a primary value within the primary integration time, and the primary value is combined with the secondary value.

Abstract: A light sensing device is provided, which includes a photodiode, a capacitor circuit and an ADC. The ADC includes a comparator, a counter, a reset switch, a logic circuit and a reference voltage switching circuit. The reference voltage switching circuit is controlled by the logic circuit to a determination reference voltage. When a primary integration time ends, a first node has a residual voltage that does not reach a reference voltage, the logic circuit controls the reference voltage switching circuit to provide the determination reference voltage to the comparator or the capacitor circuit within a secondary integration time, and the comparator outputs a comparison signal, the logic circuit receives the comparison signal within the secondary integration time, and determines the secondary value and outputs to the counter. The counter generates a primary value within the primary integration time, and the primary value is combined with the secondary value.

Abstract: A light sensor having an adaptively controlled gain includes a photoelectric element, an operational amplifier, a comparator, an adaptive gain control circuit, a variable capacitor and a pulse accumulator circuit. The photoelectric element converts light energy into a photocurrent. The operational amplifier outputs an error amplified signal based on a gain multiplied by a voltage difference between an input voltage and a reference voltage. The comparator compares the error amplified signal with a voltage of a reference voltage source to output a comparison signal. The adaptive gain control circuit includes a pulse detector circuit and a gain control circuit. The pulse detector circuit detects the comparison signal and a clock signal to output a pulse detected signal. The adaptive gain control circuit outputs a capacitance modulating signal according to the pulse detected signal. A capacitance of the variable capacitor is modulated according to the capacitance modulating signal.