Patents by Inventor Chiho KAWANABE

Chiho KAWANABE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10043913
    Abstract: A semiconductor device with favorable electrical characteristics is provided. In an oxide semiconductor film, a plurality of electron diffraction patterns are observed in such a manner that a surface over which the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm while the position of the film and the position of the electron beam are relatively moved. The electron diffraction patterns include 50 or more electron diffraction patterns observed in different areas. The sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%. The first electron diffraction patterns account for 50% or more. The first electron diffraction pattern includes observation points that are not symmetry or observation points disposed in a circular pattern. The second electron diffraction pattern includes observation points corresponding to the vertices of a hexagon.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Yuhei Sato, Yasumasa Yamane, Shunpei Yamazaki, Kenichi Okazaki, Chiho Kawanabe
  • Patent number: 10032928
    Abstract: Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: July 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Yasumasa Yamane, Yuhei Sato, Takahisa Ishiyama, Kenichi Okazaki, Chiho Kawanabe, Masashi Oota, Noritaka Ishihara
  • Patent number: 9780070
    Abstract: A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: October 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Chida, Yoshiaki Oikawa, Chiho Kawanabe
  • Publication number: 20170141233
    Abstract: Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 18, 2017
    Inventors: Akihisa SHIMOMURA, Yasumasa YAMANE, Yuhei SATO, Takahisa ISHIYAMA, Kenichi OKAZAKI, Chiho KAWANABE, Masashi OOTA, Noritaka ISHIHARA
  • Patent number: 9559174
    Abstract: Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Yasumasa Yamane, Yuhei Sato, Takahisa Ishiyama, Kenichi Okazaki, Chiho Kawanabe, Masashi Oota, Noritaka Ishihara
  • Patent number: 9406760
    Abstract: Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: August 2, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Yasumasa Yamane, Yuhei Sato, Takahisa Ishiyama, Kenichi Okazaki, Chiho Kawanabe, Masashi Oota, Noritaka Ishihara
  • Publication number: 20160197193
    Abstract: Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Akihisa SHIMOMURA, Yasumasa YAMANE, Yuhei SATO, Takahisa ISHIYAMA, Kenichi OKAZAKI, Chiho KAWANABE, Masashi OOTA, Noritaka ISHIHARA
  • Publication number: 20150333036
    Abstract: A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.
    Type: Application
    Filed: June 2, 2015
    Publication date: November 19, 2015
    Inventors: Akihiro CHIDA, Yoshiaki OIKAWA, Chiho KAWANABE
  • Patent number: 9190428
    Abstract: A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: November 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Chida, Yoshiaki Oikawa, Chiho Kawanabe
  • Publication number: 20150318359
    Abstract: A semiconductor device with favorable electrical characteristics is provided. In an oxide semiconductor film, a plurality of electron diffraction patterns are observed in such a manner that a surface over which the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm while the position of the film and the position of the electron beam are relatively moved. The electron diffraction patterns include 50 or more electron diffraction patterns observed in different areas. The sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%. The first electron diffraction patterns account for 50% or more. The first electron diffraction pattern includes observation points that are not symmetry or observation points disposed in a circular pattern. The second electron diffraction pattern includes observation points corresponding to the vertices of a hexagon.
    Type: Application
    Filed: March 17, 2015
    Publication date: November 5, 2015
    Inventors: Akihisa SHIMOMURA, Yuhei SATO, Yasumasa YAMANE, Shunpei YAMAZAKI, Kenichi OKAZAKI, Chiho KAWANABE
  • Publication number: 20150243738
    Abstract: Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed.
    Type: Application
    Filed: February 19, 2015
    Publication date: August 27, 2015
    Inventors: Akihisa SHIMOMURA, Yasumasa YAMANE, Yuhei SATO, Takahisa ISHIYAMA, Kenichi OKAZAKI, Chiho KAWANABE, Masashi OOTA, Noritaka ISHIHARA
  • Publication number: 20140248744
    Abstract: Provided is a method for manufacturing a semiconductor device, which prevents waste generation from being caused peeling of films and prevents failure of peeling from being caused by waste due to peeling of films. A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.
    Type: Application
    Filed: May 13, 2014
    Publication date: September 4, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro CHIDA, Yoshiaki OIKAWA, Chiho KAWANABE
  • Patent number: 8728868
    Abstract: Provided is a method for manufacturing a semiconductor device, which prevents waste generation from being caused peeling of films and prevents failure of peeling from being caused by waste due to peeling of films. A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Chida, Yoshiaki Oikawa, Chiho Kawanabe
  • Publication number: 20130344681
    Abstract: Provided is a method for manufacturing a semiconductor device, which prevents waste generation from being caused peeling of films and prevents failure of peeling from being caused by waste due to peeling of films. A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.
    Type: Application
    Filed: August 8, 2013
    Publication date: December 26, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro CHIDA, Yoshiaki OIKAWA, Chiho KAWANABE
  • Patent number: 8507322
    Abstract: Provided is a method for manufacturing a semiconductor device, which prevents waste generation from being caused peeling of films and prevents failure of peeling from being caused by waste due to peeling of films. A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 13, 2013
    Inventors: Akihiro Chida, Yoshiaki Oikawa, Chiho Kawanabe
  • Publication number: 20110318881
    Abstract: Provided is a method for manufacturing a semiconductor device, which prevents waste generation from being caused peeling of films and prevents failure of peeling from being caused by waste due to peeling of films. A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 29, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Akihiro CHIDA, Yoshiaki OIKAWA, Chiho KAWANABE